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74LVCV2G66DC データシート(PDF) 10 Page - NXP Semiconductors |
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74LVCV2G66DC データシート(HTML) 10 Page - NXP Semiconductors |
10 / 23 page 74LVCV2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 16 June 2010 10 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 11.1 Waveforms and test circuit Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Input (nY or nZ) to output (nZ or nY) propagation delays 001aaa541 tPLH tPHL VM VM VM VM nY or nZ input nZ or nY output GND VI VOH VOL Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. Enable and disable times 001aaa542 tPLZ tPHZ switch disabled switch enabled switch enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nE input nY or nZ nY or nZ VI VOL VOH VCC VM VM VX VY VM GND GND tPZL tPZH Table 10. Measurement points Supply voltage Input Output VCC VM VM VX VY 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL +0.1VCC VOH − 0.1VCC 2.7V 1.5V 1.5V VOL +0.3 V VOH − 0.3 V 3.0V to 3.6V 1.5V 1.5V VOL +0.3 V VOH − 0.3 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VOL +0.3 V VOH − 0.3 V |
同様の部品番号 - 74LVCV2G66DC |
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同様の説明 - 74LVCV2G66DC |
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