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ISL22426 データシート(PDF) 10 Page - Intersil Corporation |
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ISL22426 データシート(HTML) 10 Page - Intersil Corporation |
10 / 15 page 10 FN6180.2 September 8, 2009 Pin Description Potentiometer Pins RHI AND RLI (i = 0, 1) The high (RHi) and low (RLi) terminals of the ISL22426 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWI (i = 0, 1) RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SHDN The SHDN pin forces the resistor to end-to-end open circuit condition on RHi and shorts RWi to RLi. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically ANDed with SHDN bit in ACR register. SPI interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. Bus Interface Pins SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. SERIAL DATA OUTPUT (SDO) The SDO is an open drain serial data output pin. During a read cycle, the data bits are shifted out at the falling edge of the serial clock SCK, while the CS input is low. SDO requires an external pull-up resistor for proper operation. SERIAL DATA INPUT (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI external host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. CHIP SELECT (CS) CS LOW enables the ISL22426, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22426 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. Principles of Operation The ISL22426 is an integrated circuit incorporating two DCPs with its associated registers, non-volatile memory and the SPI serial interface providing direct communication between host and potentiometers and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h FIGURE 14. LARGE SIGNAL SETTLING TIME Typical Performance Curves (Continued) SIGNAL AT WIPER (WIPER UNLOADED) WIPER MID POINT MOVEMENT FROM 3Fh TO 40h SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) SCL RLi RWi RHi FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE ISL22426 |
同様の部品番号 - ISL22426 |
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同様の説明 - ISL22426 |
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