ISL12024 datasheet(4/25 Pages) INTERSIL

部品番号	ISL12024

部品情報	Real-Time Clock/Calendar with Embedded Unique ID

Download	25 Pages

Scroll/Zoom	100%

メーカー	INTERSIL [Intersil Corporation]

ホームページ	http://www.intersil.com/cda/home

Logo

4 / 25 page

4

FN6370.1

October 18, 2006

EEPROM Specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

EEPROM Endurance

2,000,000

Cycles

EEPROM Retention

Temperature

≤ +75°C

50

Years

Serial Interface (I2C) Specifications

DC Electrical Specifications

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VIL

SDA, and SCL Input Buffer LOW

Voltage

-0.3

0.3 x VDD

V

VIH

SDA, and SCL Input Buffer HIGH

Voltage

0.7 x VDD

VDD + 0.3

V

Hysteresis

SDA and SCL Input Buffer Hysteresis

0.05 x VDD

V

VOL

SDA Output Buffer LOW Voltage

IOL = 4mA

0

0.4

V

ILI

Input Leakage Current on SCL

VIN = 5.5V

100

nA

ILO

I/O Leakage Current on SDA

VIN = 5.5V

100

nA

AC Electrical Specifications

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

fSCL

SCL Frequency

400

kHz

tIN

Pulse width Suppression Time at SDA

and SCL Inputs

Any pulse narrower than the max spec

is suppressed.

50

ns

tAA

SCL Falling Edge to SDA Output Data

Valid

SCL falling edge crossing 30% of

VDD, until SDA exits the 30% to 70%

of VDD window.

900

ns

tBUF

Time the Bus Must be Free Before the

Start of a New Transmission

SDA crossing 70% of VDD during a

STOP condition, to SDA crossing 70%

of VDD during the following START

condition.

1300

ns

tLOW

Clock LOW Time

Measured at the 30% of VDD

crossing.

1300

ns

tHIGH

Clock HIGH Time

Measured at the 70% of VDD

crossing.

600

ns

tSU:STA

START Condition Setup Time

SCL rising edge to SDA falling edge.

Both crossing 70% of VDD.

600

ns

tHD:STA

START Condition Hold Time

From SDA falling edge crossing 30%

of VDD to SCL falling edge crossing

70% of VDD.

600

ns

tSU:DAT

Input Data Setup Time

From SDA exiting the 30% to 70% of

VDD window, to SCL rising edge

crossing 30% of VDD.

100

ns

tHD:DAT

Input Data Hold Time

From SCL rising edge crossing 70% of

VDD to SDA entering the 30% to 70%

of VDD window.

0ns

tSU:STO

STOP Condition Setup Time

From SCL rising edge crossing 70% of

VDD, to SDA rising edge crossing

30% of VDD.

600

ns

tHD:STO

STOP Condition Hold Time for Read,

or Volatile Only Write

From SDA rising edge to SCL falling

edge. Both crossing 70% of VDD.

600

ns

ISL12024

同様の部品番号 - ISL12024

メーカー	部品番号	データシート	部品情報
Intersil Corporation	ISL12024	768Kb / 6P	High-Accuracy RTC Modules, Feature-Rich RTCs
Intersil Corporation	ISL12024	9Mb / 44P	Providing high-performance solutions for every link in the signal chain
Renesas Technology Corp	ISL12024	1,018Kb / 25P	Real-Time Clock/Calendar with Embedded Unique ID
Renesas Technology Corp	ISL12024IBZ	1,018Kb / 25P	Real-Time Clock/Calendar with Embedded Unique ID
Intersil Corporation	ISL12024IRTC	426Kb / 24P	Real-Time Clock/Calendar with Embedded Unique ID December 15, 2011

More results

同様の説明 - ISL12024

メーカー	部品番号	データシート	部品情報
Intersil Corporation	ISL12024IRTC	426Kb / 24P	Real-Time Clock/Calendar with Embedded Unique ID December 15, 2011
Intersil Corporation	ISL12024IRTCZ	359Kb / 24P	Real-Time Clock/Calendar with Embedded Unique ID
Renesas Technology Corp	ISL12024	1,018Kb / 25P	Real-Time Clock/Calendar with Embedded Unique ID
Renesas Technology Corp	ISL12024IRTC	974Kb / 24P	Real-Time Clock/Calendar with Embedded Unique ID
Microchip Technology	MCP79410	1Mb / 60P	Battery-Backed I2C??Real-Time Clock/Calendar with EEPROM and Unique ID 11/29/12 2010-2013
	MCP79400	574Kb / 38P	I2C??Real-Time Clock/Calendar with SRAM, Unique ID and Battery Switchover 2011
	MCP79400T-I	1Mb / 42P	I2C Real-Time Clock/Calendar with SRAM, Unique ID and Battery Switchover 11/29/11
	MCP79410	580Kb / 38P	I2C??Real-Time Clock/Calendar with EEPROM, SRAM, Unique ID and Battery Switchover 2011
NXP Semiconductors	PCF8563	466Kb / 45P	Real-time clock/calendar Rev. 9-16 June 2011
NXP Semiconductors	PCF8563TF4.118	492Kb / 50P	Real-time clock/calendar Rev. 10-3 April 2012