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ISL54502IRUZ-T データシート(PDF) 8 Page - Intersil Corporation |
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ISL54502IRUZ-T データシート(HTML) 8 Page - Intersil Corporation |
8 / 13 page 8 FN6550.2 October 26, 2009 Detailed Description The ISL54501 and ISL54502 are bi-directional, single pole/single throw (SPST) analog switches. They offer precise switching capability from a single 1.8V to 5.5V supply with low ON-resistance and high speed operation. With a single supply of 5V the typical ON-resistance is only 5Ω, with a typical turn-on and turn-off time of: tON = 22ns, tOFF = 15ns. The devices are especially well suited for portable battery powered equipment due to their low operating supply voltage (1.8V), low power consumption (0.11µW), low leakage currents (300nA max), and tiny µTDFN package. The ISL54501 is a single normally open (NO) SPST analog switch. The ISL54502 is a single normally closed (NC) SPST analog switch. External V+ Series Resistor For improved ESD and latch-up immunity, Intersil recommends adding a 100Ω resistor in series with the V+ power supply pin of the ISL54501, ISL54502 IC (see Figure 6). During an overvoltage transient event (such as occurs during system level IEC 61000 ESD testing), substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the V+ power supply to ground. This will result in a significant amount of current flow in the IC, which can potentially create a latch-up state or permanently damage the IC. The external V+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many over voltage transient events. Under normal operation the sub-microamp IDD current of the IC produces an insignificant voltage drop across the 100Ω series resistor resulting in no impact to switch operation or performance. Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 7). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold FIGURE 5. CAPACITANCE TEST CIRCUIT Test Circuits and Waveforms (Continued) V+ C GND NO OR NC COM IN IMPEDANCE ANALYZER VINL OR VINH FIGURE 6. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY IN COM 100Ω NO NC V+ GND C OPTIONAL PROTECTION RESISTOR ISL54501, ISL54502 |
同様の部品番号 - ISL54502IRUZ-T |
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同様の説明 - ISL54502IRUZ-T |
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