データシートサーチシステム |
|
ISL45042IR-T データシート(PDF) 8 Page - Intersil Corporation |
|
ISL45042IR-T データシート(HTML) 8 Page - Intersil Corporation |
8 / 8 page 8 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6072.8 July 9, 2008 ISL45042 Thin Dual Flat No-Lead Plastic Package (TDFN) // NX (b) SECTION "C-C" 5 (A1) BOTTOM VIEW A 6 AREA INDEX C C 0.10 0.08 SIDE VIEW 0.15 2X E A B C 0.15 D TOP VIEW CB 2X 6 8 AREA INDEX NX L E2 E2/2 REF. e N (Nd-1)Xe (DATUM A) (DATUM B) 5 0.10 8 7 D2 B A M C N-1 12 PLANE SEATING C A A3 NX b D2/2 NX k FOR EVEN TERMINAL/SIDE e C L TERMINAL TIP L1 10 L L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE SYMBOL MILLIMETERS NOTES MIN NOMINAL MAX A 0.70 0.75 0.80 - A1 - 0.02 0.05 - A3 0.20 REF - b 0.25 0.30 0.35 5, 8 D 3.00 BSC - D2 2.20 2.30 2.40 7, 8, 9 E 3.00 BSC - E2 1.40 1.50 1.60 7, 8, 9 e 0.65 BSC - k0.25 - - - L 0.20 0.30 0.40 8 N8 2 Nd 4 3 Rev. 3 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-WEEC-2 except for the “L” min dimension. |
同様の部品番号 - ISL45042IR-T |
|
同様の説明 - ISL45042IR-T |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |