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74AHC259 データシート(PDF) 4 Page - NXP Semiconductors |
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74AHC259 データシート(HTML) 4 Page - NXP Semiconductors |
4 / 17 page 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 4 of 17 NXP Semiconductors 74AHC259; 74AHCT259 8-bit addressable latch 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. Q6 11 latch output Q7 12 latch output D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) VCC 16 supply voltage Table 2. Pin description …continued Symbol Pin Description Table 3. Function table[1] Operating mode Input Output MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Reset (clear) L H XXXX LLLLLLLL Demultiplexer (active HIGH 8-channel) decoder (when D = H) LLdLLLQ = d LLLLLLL d H L L L Q = d LLLLLL d L H L LLQ = d LLLLL d H H L LLLQ = d LLLL dLLH LLLLQ = d LLL d H L H LLLLLQ = d LL d L H H LLLLLLQ = d L d H H H LLLLLLLQ = d Memory (no action) H H XXXXq0 q1 q2 q3 q4 q5 q6 q7 Addressable latch H LdLLLQ = d q1 q2 q3 q4 q5 q6 q7 dH LLq0 Q=d q2 q3 q4 q5 q6 q7 dLH Lq0 q1 Q=d q3 q4 q5 q6 q7 d HHL q0 q1 q2 Q=d q4 q5 q6 q7 dLLH q0 q1 q2 q3 Q=d q5 q6 q7 dH LH q0 q1 q2 q3 q4 Q=d q6 q7 d L HHq0 q1 q2 q3 q4 q5 Q=d q7 HHHHq0 q1 q2 q3 q4 q5 q6 Q=d |
同様の部品番号 - 74AHC259_08 |
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同様の説明 - 74AHC259_08 |
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