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SI5338K-A-GM データシート(PDF) 6 Page - Silicon Laboratories |
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SI5338K-A-GM データシート(HTML) 6 Page - Silicon Laboratories |
6 / 170 page Si5338 6 Rev. 0.6 Table 5. Performance Characteristics (VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit PLL Acquisition Time tACQ —— 25 ms PLL Lock Range fLOCK 5000 — — ppm PLL Loop Bandwidth fBW —1.6 — MHz MultiSynth Frequency Synthesis Resolution fRES Output frequency < Fvco/8 0 0 1 ppb CLKIN Loss of Signal Detect Time tLOS —2.6 5 µs CLKIN Loss of Signal Release Time tLOSRLS 0.01 0.2 1 µs PLL Loss of Lock Detect Time tLOL —5 10 ms POR to Output Clock Valid (Pre-programmed Devices) tRDY —— 2 ms Input-to-Output Propagation Delay tPROP Buffer Mode (PLL Bypass) —2.5 — ns Output-Output Skew tDSKEW Rn divider = 11 —— 100 ps POR to I2C Ready —— 15 ms Programmable Initial Phase Offset POFFSET –45 — +45 ns Phase Increment/Decrement Accuracy PSTEP —— 20 ps Phase Increment/Decrement Range PRANGE –45 — +45 ns Frequency range for phase increment/decrement fPRANGE —— 3502 MHz Phase Increment/Decrement Update Time PUPDATE Pin control2,3 MultiSynth output >18 MHz 667 — — ns Notes: 1. Outputs at integer-related frequencies and using the same driver format. See "3.9.3. Initial Phase Offset" on page 24. 2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept between 5 MHz and Fvco/8. 3. Update rate via I2C is also limited by the time it takes to perform a write operation. 4. Default value is 0.5% down spread. 5. Default value is ~31.5 kHz. |
同様の部品番号 - SI5338K-A-GM |
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同様の説明 - SI5338K-A-GM |
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