ADC1410S065 datasheet(28/35 Pages) NXP

部品番号	ADC1410S065

部品情報	Single 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

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メーカー	NXP [NXP Semiconductors]

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28 / 35 page

ADC1410S065_080_105_125_2

Objective data sheet

Rev. 02 — 4 June 2009

28 of 35

NXP Semiconductors

ADC1410S065/080/105/125

Single 14-bit ADC 65, 80, 105 or 125 Msps

1 to 0 DATA_FORMAT

R/W

output data format

00

offset binary

01

2’s complement

10

gray code

11

offset binary

Table 22.

Output clock register (address 0012h) bit description

Bit

Symbol

Access

Value Description

7 to 4 reserved

3

DAVINV

R/W

output clock data valid (DAV) polarity

0

normal

1

inverted

2 to 0 DAVPHASE

R/W

DAV phase select

000

output clock shifted (ahead) by 3 ns

001

output clock shifted (ahead) by 2.5 ns

010

output clock shifted (ahead) by 2 ns

011

output clock shifted (ahead) by 1.5 ns

100

output clock shifted (ahead) by 1 ns

101

output clock shifted (ahead) by 0.5 ns

110

default value as deﬁned in timing section

111

output clock shifted (delayed) by 0.5 ns

Table 23.

Offset register (address 0013h) bit description

Bit

Symbol

Access

Value

Description

7 to 6 reset

5 to 0 DIG_OFFSET

R/W

digital offset adjustment

011111

+31 LSB

...

000000

0

...

100000

−32 LSB

Table 21.

Output data standard control register (address 0011h) bit description …continued

Bit

Symbol

Access

Value

Description

同様の部品番号 - ADC1410S065

メーカー	部品番号	データシート	部品情報
Integrated Device Techn...	ADC1410S065HN-C1	539Kb / 38P	Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs
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同様の説明 - ADC1410S065

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