データシートサーチシステム |
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LM3414HVSD データシート(PDF) 7 Page - National Semiconductor (TI) |
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LM3414HVSD データシート(HTML) 7 Page - National Semiconductor (TI) |
7 / 20 page Symbol Parameter Conditions Min Typ Max Units T SD-HYS Thermal Shutdown Temperature Hysteresis T J Falling 10 °C THERMAL RESISTANCE θ JA Junction to Ambient, ePSOP-8 package 45 °C/W 0 LFPM Air Flow (Note 3) LLP-8 package 54 °C/W Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The human body model is a 100pF capacitor discharged through a 1.5 k Ω resistor into each pin. Note 3: Tested on a 4 layer JEDEC board. Four vias provided under the exposed pad. See JESD51-5 and JESD51-7. The value of the θ JA for the LLP package is specifically dependent on the PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the LLP package, refer to Application Note AN-1187. Note 4: Typical specification represent the most likely parametric norm at 25°C operation. Note 5: VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading to the pin. 7 www.national.com |
同様の部品番号 - LM3414HVSD |
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同様の説明 - LM3414HVSD |
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