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ISL29030A データシート(PDF) 5 Page - Intersil Corporation |
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ISL29030A データシート(HTML) 5 Page - Intersil Corporation |
5 / 16 page ISL29030A 5 FN7722.0 November 18, 2010 tLOW LOW Period of the SCL Clock Measured at the 30% of VDD crossing 1300 ns tHIGH HIGH period of the SCL Clock 600 ns tSU:STA Set-up Time for a Repeated START Condition 600 ns tHD:DAT Data Hold Time 30 ns tSU:DAT Data Set-up Time 100 ns tR Rise Time of both SDA and SCL Signals (Note 11) 20 + 0.1xCb ns tF Fall Time of both SDA and SCL Signals (Note 11) 20 + 0.1xCb ns tSU:STO Set-up Time for STOP Condition 600 ns tBUF Bus Free Time Between a STOP and START Condition 1300 ns Cb Capacitive Load for Each Bus Line 400 pF Rpull-up SDA and SCL system bus pull-up resistor Maximum is determined by tR and tF 1kΩ tVD;DAT Data Valid Time 0.9 µs tVD:ACK Data Valid Acknowledge Time 0.9 µs VnL Noise Margin at the LOW Level 0.1VDD V VnH Noise Margin at the HIGH Level 0.2VDD V NOTES: 10. I2C limits are based on design/simulation and are not production tested. 11. Cb is the capacitance of the bus in pF. I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance (Note 10). (Continued) PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT FIGURE 1. I2C TIMING DIAGRAM |
同様の部品番号 - ISL29030A |
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同様の説明 - ISL29030A |
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