データシートサーチシステム |
|
LS7211N データシート(PDF) 2 Page - LSI Computer Systems |
|
LS7211N データシート(HTML) 2 Page - LSI Computer Systems |
2 / 8 page TRIGGER Input (TRIG, Pin 18) A transition at the TRIG input causes OUT to switch with or without delay, depending on the selected mode. The TRIG in- put to OUT transition relation is always opposite in polarity, with the exception of One-Shot mode. (See Mode definitions above.) TRIG input has an internal pull-down resistor of about 500kΩ and is buffered by a Schmitt trigger to provide input hysteresis. LS7211N TIME BASE Input (RC/CLOCK, Pin 4) For LS7211N, the basic timing signal is applied at the RC/ CLOCK input. The clock can be provided from either an ex- ternal source or generated by an internal oscillator by con- necting an R-C network to this input. The frequency of oscillation is given by ƒ 1/RC. Chip-to- chip oscillation tolerance is ± 5% for a fixed value of RC. The minimum resistance, R MIN = 4000Ω, VDD = + 4V = 1200Ω, VDD = +10V = 600Ω, VDD = +18V The external clock mode is selected by applying a logic low to the RCS/CLKS input (Pin 5); the internal oscillator mode is selected by applying a high level to the RCS/CLKS input. LS7212N TIME BASE Input (XTLI/CLOCK, Pin 4) For LS7212N, the basic timing clock is applied to the XLTI/ CLOCK input from either an external clock source or gener- ated by an internal crystal oscillator by connecting a crystal between XTLI/CLOCK input and the XTLO output (Pin 5). LS7211N TIME BASE SELECT Input (RCS/CLKS, Pin 5) For LS7211N, the external clock operation at Pin 4 is se- lected by applying a logic low to the RCS/CLKS input. The in- ternal oscillator option with RC timer at Pin 4 is selected by applying a logic high at the RCS/CLKS input. RCS/CLKS in- put has an internal pull-down resistor of about 500kΩ. LS7212N TIME BASE Output (XTLO, Pin 5) For LS7212N, when a crystal is used for generating the time base oscillation, the crystal is connected between XTLI/ CLOCK and XTLO pins. PRESCALER SELECT Input (PSCLS, Pin 6) The PSCLS input is a 3-state input, which selects one of three prescale factors according to Table 2. TABLE 2. PRESCALE FACTOR SELECTION PSCLS Input S (Prescale Factor ) Logic Level LS7211N LS7212N Float 1 1 VSS 3,000 32,768 VDD 3,600 32,768x60 Using prescale factors of 3000 and 3600, delays in units of minutes can be produced from 50Hz and 60Hz line sources. Prescale factors of 32,768 and 32,768 x 60 can be used to generate accurate delays in units of seconds and minutes, respectively, from a 32kHz watch crystal. 7211N-062209-2 TIMER RESET Input (RESET, Pin 7) When RESET input switches high, any timeout in progress is aborted and OUT switches high without delay. With RE- SET high, OUT remains high. When RESET switches low with TRIG low in any mode, OUT remains high. When RE- SET switches low with TRIG high in Delayed Operate and Dual Delay modes, the delay timer is started and OUT switches low at the end of the delay timeout. When RE- SET switches low with TRIG high in Delayed Release mode, OUT switches low without delay. When RESET switches low with TRIG high in One-Shot mode, OUT re- mains high. RESET input has an internal pull-down resistor of about 500kΩ, and is buffered by a Schmitt Trigger to provide input hysteresis. VSS (-V, Pin 8) Supply voltage negative terminal or GND. DELAY Output (OUT, Pin 9) Except in One-Shot mode, OUT switches with or without delay (depending on mode) in inverse relation to the logic level of the TRIG input. In One-Shot mode, a timed low level is produced at OUT, in response to a positive transi- tion of the TRIG input. WEIGHTING BIT Inputs (WB7 to WB0, Pins 10 - 17) Inputs WB0 through WB7 are binary weighted delay bits used to program the delay according to the following relations: One-Shot Mode: Pulse width = SW ƒ All other Modes: Delay = SW + 0.5 ƒ Where: S = Prescale factor (See Table 2) ƒ = Time base frequency at Pin 4 W = WB0 + WB1 + ....... WB7 The weighting factor W is calculated by substituting in the equation above for W, the weighted values for all the WB inputs that are at logic high. The weighted values for the WB inputs are shown in Table 3. Each WB input has an in- ternal pull-down resistor of about 500kΩ. TABLE 3. BIT WEIGHTS BITS VALUE WB0 1 WB1 2 WB2 4 WB3 8 WB4 16 WB5 32 WB6 64 WB7 128 VDD (+V, Pin 3) Supply voltage positive terminal. |
同様の部品番号 - LS7211N |
|
同様の説明 - LS7211N |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |