データシートサーチシステム |
|
LS7215 データシート(PDF) 5 Page - LSI Computer Systems |
|
LS7215 データシート(HTML) 5 Page - LSI Computer Systems |
5 / 8 page A B D C E F G H OUT(DD) OUT(DR) OUT(DO) OUT(OS) RESET TRIG Note 1. TRIG input is clocked in by the negative edge of external clock. Note 2. Inputs A, B are sampled only at a TRIG input transition and ignored at all other times. Note 3. OUT is switched by the positive edge of the external clock. FIGURE 3. INPUT/OUTPUT TIMING A. Turn-on delay in DO and DD modes; Pulse-width in OS mode. B. Turn-off delay in DR and DD modes. C. Pulse-width extended by re-trigger in OS mode. No effect in DO and DD modes because TRIG switches back low before turn-on delay has timed out. D. Turn-off delay in DR mode. E. Turn-on delay in DO and DD modes; pulse-width in OS mode. F. No effect in DO, DR and DD modes because of TRIG’s switching back to opposite levels. G. Time-outs aborted and OUT forces high by RESET. H. After the removal of RESET, OUT switches to the inverse polarity of TRIG immediately (DR) or after the timeout (DO, DD). No effect in OS. FIGURE 4. MODE ILLUSTRATION WITH TRIG, OUT AND RESET 7215-040307-5 t1 t2 Delayed Operate Mode Programmed Delay Immediate Release t4 Clock TRIG A, B WB0-WB7 OUT t0 WB0-WB7 (Internal) LOAD Data Latched |
同様の部品番号 - LS7215 |
|
同様の説明 - LS7215 |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |