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LS7216 データシート(PDF) 1 Page - LSI Computer Systems |
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LS7216 データシート(HTML) 1 Page - LSI Computer Systems |
1 / 8 page PROGRAMMABLE DIGITAL DELAY TIMER DESCRIPTION: The LS7215 and LS7216 are CMOS integrated circuits for gener- ating digitally programmable delays. The delay is controlled by 8 bi- nary weighted inputs, WB0 - WB7, in conjunction with an applied clock or oscillator frequency. The programmed time delay man- ifests itself in the Delay Output (OUT) as a function of the Oper- ating Mode selected by the Mode Select inputs A and B: One-Shot, Delayed Operate, Delayed Release or Dual Delay. The time de- lay is initiated by a transition at the Trigger Input (TRIG). I/O DESCRIPTION: MODE SELECT Inputs A & B (Pins 1 & 2) The 4 operating modes are selected by Inputs A and B according to Table 1 TABLE 1. MODE SELECTION A B MODE 0 0 One-Shot (OS) 0 1 Delayed Operate (DO) 1 0 Delayed Release (DR) 1 1 Dual Delay (DD) Each input has an internal pull-up resistor of about 500kΩ. One-Shot Mode (OS) A positive transition at the TRIG input causes OUT to switch low without delay and starts the delay timer. At the end of the pro- grammed delay timeout, OUT switches high. If a delay timeout is in progress when a positive transition occurs at the TRIG input, the delay timer will be restarted. A negative transition at the TRIG input has no effect. Delayed Operate Mode (DO) A positive transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches low. A negative transition at the TRIG input causes OUT to switch high without delay. OUT is high when TRIG is low. Delayed Release Mode (DR) A negative transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches high. A pos- tive transition at the TRIG input causes OUT to switch low without delay. OUT is low when TRIG is high. Dual Delay Mode (DD) A positive or negative transition at the TRIG input starts the delay timer. At the end of the delay timeout, OUT switches to the logic state which is the inverse of the TRIG input. If a de- lay timeout is in progress when a transition occurs at the TRIG input, the delay timer is restarted. 7215-072009-1 July 2009 LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 LS7215 LS7216 FEATURES: • Programmable delay from microseconds to days • Programmable delay controlled by 8 binary-weighted delay inputs that can be latched from a shared 8-bit bus • On chip oscillator (RC or Crystal) or external clock time base • Selectable prescaler for real time delay generation based on 50Hz/60Hz time base or 32,768Hz watch crystal • Four operating modes • Reset input for delay abort • Low quiescent and operating current • Direct relay drive • +3V to +18V operation (VDD - VSS) • LS7215, LS7216 (DIP); LS7215-S, LS7216-S (SOIC) - See Figure 1 - UL ® A3800 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20 V DD (+V) A B TRIG RC/CLOCK PSCLS RESET VSS (-V) WB0 WB1 WB2 WB3 WB4 WB5 WB6 WB7 OUT 1 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20 VDD (+V) A B TRIG XTLI/CLOCK XTLO PSCLS RESET V SS (-V) WB0 WB1 WB2 WB3 WB4 WB5 WB6 WB7 OUT FIGURE 1 PIN ASSIGNMENT - TOP VIEW RCS/CLKS 10 11 LOAD 10 11 LOAD 2 OD OUT OD OUT |
同様の部品番号 - LS7216 |
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同様の説明 - LS7216 |
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