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データシートサーチシステム |
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データシートサーチシステム |
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33880 データシート(PDF) 9 Page - Freescale Semiconductor, Inc |
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33880 データシート(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 25 page  Analog Integrated Circuit Device Data Freescale Semiconductor 9 33880 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS Figure 5. SPI Timing Diagram Figure 6. Valid Data Delay Time and Valid Time Test Circuit Figure 7. Enable and Disable Time Test Circuit Figure 8. Switching Time Test Circuit tDO(DIS) 0.7 VDD 0.2 VDD 0.2 VDD 0.7 VDD 0.2 VDD tLEAD tDI(SU) tDI(HOLD) tVALID tLAG CS SCLK DI DO MSB in MSB out LSB out 0.7 VDD 0.2 VDD tDO(EN) DO CL = 200 pF VDD = 5.0 V SCLK 33880 Under Test NOTE: CL represents the total capacitance of the test fixture and probe. DO CL = 200 pF RL = 1.0 kΩ CS 33880 Under Test NOTE: CL represents the total capacitance of the test fixture and probe. VDD = 5.0 V VPull-Up = 2.5 V Output CL RL = 620 Ω VPWR = 13 V CS 33880 Under Test NOTE: CL represents the total capacitance of the test fixture and probe. VDD = 5.0 V |
同様の部品番号 - 33880 |
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同様の説明 - 33880 |
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