LC863332/28/24/20/16A

No.6695-4/20

- Interrupt priority control

Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible.

Low or high

priority can be assigned to the interrupts from 3 to 9 listed above.

For the external interrupt INT0 and INT1, high

or highest priority can be set.

(14) Sub-routine stack level

- A maximum of 128 levels (stack is built in the internal RAM)

(15) Multiplication/division instruction

- 16 bits

× 8 bits (7 instruction cycle times)

- 16 bits / 8 bits (7 instruction cycle times)

(16) 3 oscillation circuits

- Built-in RC oscillation circuit used for the system clock

- Built-in VCO circuit used for the system clock and OSD

- X’tal oscillation circuit used for base timer, system clock and PLL reference

(17) Standby function

- HALT mode

The HALT mode is used to reduce the power dissipation.

In this operation mode, the program execution is

stopped.

This mode can be released by the interrupt request or the system reset.

- HOLD mode

The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations.

This mode can be

released by the following conditions.

• Pull the reset terminal ( RES ) to low level.

• Feed the selected level to either P70/INT0 or P71/INT1.

• Input the interrupt condition to Port 0.

(18) Package

- DIP42S

- QIP48E

(19) Development tools

- Flash EEPROM:

LC86F3348A

- Evaluation chip:

LC863096

- Emulator:

EVA86000 (main) + ECB863200 (evaluation chip board)

+ POD863300 (pod: DIP42S) or POD863301 (QIP48E)