The analog signal (AIN) is acquired on the falling edge of the clock input (CLK). The acquired analog signal is

converted to a digital code and is output from the digital outputs (D8 to D1, OF) on the clock falling edge delayed three

clock cycles from the clock cycle in which the analog signal was acquired.

No. 5428-3/6

LC89086M

Timing Chart

TWH

TWL

TAP

Td

1.5 V

1.5 V

N

N + 1

N + 2

N + 3

N – 4

N – 3

N –2

N – 1

N

Clock input

(CLK)

Analog input

(AIN)

Digital output

(D8 to D1,OF)

TOE

High impedance

1.5V

Output enable input

(OEB)

Digital output

(D8 to D1,OF)

TOD

A09018

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Resolution

Res

8

bit

Maximum conversion rate

Fs

20

MSPS

Linearity error

LE

DC accuracy

±1.0

LSB

Differential linearity error

DLE

DC accuracy

±1.0

LSB

Offset voltage

DC accuracy

10

50

90

mV

Power dissipation

Pd

Fs = 20 MSPS

150

220

mW

Electrical AC Characteristics 2

at Ta = 25

°C, AV

Note: Test circuits must conform to the sample application circuit.