PS No. 5241-11/11

LC895125Q, 895125W

This catalog provides information as of February, 1996. Specifications and information herein are subject to

change without notice.

s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace

equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of

which may directly or indirectly cause injury, death or property loss.

s Anyone purchasing any products described or contained herein for an above-mentioned use shall:

ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all

damages, cost and expenses associated with such use:

 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees

jointly or severally.

s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for

volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied

regarding its use or any infringements of intellectual property rights or other rights of third parties.

5. CD DSP Data Pins

• BCK, SDATA, LRCK, C2PO (input)

The LC895125 reads in CD-ROM data over these pins connected to a CD DSP.

C2PO is the C2 flag pin.

6. Other Pins

• ZRESET (input)

Reset input to the LC895125. The LC895125 is reset by a low-level input.

This pin must be held low for a period of at least 1 µs when power is first applied.

• XTALCK0, XTAL0

The main clock for the ECC and SCSI blocks. These pins support frequencies from 16.9344 to 25 MHz.

When a double-frequency input is used, these pins accept frequencies up to 38 MHz.

Use a double-frequency input when a ceramic oscillator and DRAM are used.

(This is because the internal clock must have a 50% duty.)

An external clock may input to the XTALCK pin.

The SCSI block main clock can also be provided from XTALCK1 and XTAL1 if so specified by the setting of

X1EN (pin 89).

• XTALCK1, XTAL1

The main clock for the ECC and SCSI blocks. These pins are enabled for oscillator operation by setting X1EN (pin

89). The LC895125 is designed so that the ECC and SCSI blocks can also be operated asynchronously.

This means that precise 10-MB/s synchronous transfers can be achieved by providing a 20-MHz input to

XTALCK1 and XTAL1.

A ceramic oscillator may be used here since only the rising edge of this signal is used.

• X1EN (input)

Set this pin to 1 to us use XTALCK1 and XTAL1 for the SCSI block main clock.

Set this pin to 0 to drive both the ECC and SCSI blocks from XTALCK0 and XTAL0.

• MCK (output)

Outputs either the XTALCK0 frequency or that frequency divided by 2. This pin’s output can also be stopped if

desired.