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ISL24202IRTZ-EVALZ データシート(PDF) 8 Page - Intersil Corporation |
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ISL24202IRTZ-EVALZ データシート(HTML) 8 Page - Intersil Corporation |
8 / 12 page ISL24202 8 FN7587.0 March 15, 2011 Assuming that the IOUT(MIN) = 0 instead of ISTEP, the expression in Equation 14 simplifies to: OUT Pin Leakage Current When the voltage on the OUT pin is greater than 10V, an additional leakage current flows into the pin in addition to the ISET current. Figure 6 shows the ISET current and the OUT pin current for OUT pin voltage up to 19V. In applications where the voltage on the OUT pin will be greater than 10V, the actual output voltage will be lower than the voltage calculated by Equation 8 due to this extra current. The graph in Figure 6 was measured with RSET = 4.99kΩ. Power Supply Sequence The recommended power supply sequencing is shown in Figure 7. When applying power, VDD should be applied before or at the same time as AVDD. The minimum time for tVS is 0µs. When removing power, the sequence of VDD and AVDD is not important. Do not remove VDD or AVDD within 100ms of the start of the EEPROM programming cycle. Removing power before the EEPROM programming cycle is completed may result in corrupted data in the EEPROM. Operating and Programming Supply Voltage and Current To program the EEPROM, AVDD must be ≥10.8V. If further programming is not required, the ISL24202 will operate over an AVDD range of 4.5V to 19V. During EEPROM programming, IDD and IAVDD will temporarily be 4-5x higher for up to 100ms (tPROG). Up/Down Counter Interface The ISL24202 allows the adjustment of the output VCOM voltage and the programming of the non-volatile memory through a single pin (CTL) when the CE (counter enable) pin is high. The CTL pin is biased so that its voltage is set to VDD/2 if the driving circuit is set to Tri-state or High Impedance (Hi-Z), allowing up/down operation using common digital I/O logic. CTL Pin When a mid-high-mid transition is detected on the CTL pin (see Figure 11), the internal register value counts down by one at the trailing (high-mid) edge, and the output VCOM voltage is increased according to Equation 8. Similarly, when a mid-low-mid transition is detected on the CTL pin, the internal register value counts up by one at the trailing (low-mid) edge, and the output VCOM voltage is decreased. Once the maximum or minimum value is reached, the counter saturates and will not overflow or underflow beyond those values. CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counts when the CE pin is high. Figure 8 shows a simple debouncing circuit consisting of a series 1k Ω resistor and a shunt 0.01µF capacitor connected on the CTL pin. To avoid unintentional adjustment, the ISL24202 guarantees to reject CTL pulses shorter than 20µs. This pin is pulled above 4.9V to program the EEPROM. See “Programming the EEPROM” on page 9 for details. After CE (Counter Enable) is asserted and after programming EEPROM, the very first CTL pulse is ignored (see Figure 11) to avoid the possibility of a false count (since CTL state may be unknown after programming). CE Pin To change the counter controlling the output voltage, the CE (Counter Enable) pin must be pulled high (VDD). When the CE pin is pulled low, the counter value is loaded from EEPROM, which takes 10ms (during which the inputs should remain constant). The CE pin has an internal pull-down to keep it at a logic low VCOMSPAN R1 R ⋅ 2 R1 R2 + -------------------- ⎝⎠ ⎜⎟ ⎛⎞ AVDD 20RSET -------------------- ⎝⎠ ⎜⎟ ⎛⎞ R1 R ⋅ 2 R1 R2 + -------------------- ⎝⎠ ⎜⎟ ⎛⎞ IDVROUT MAX () == (EQ. 15) FIGURE 6. OUT PIN LEAKAGE CURRENT 0 2468 10 12 14 16 18 20 OUT PIN VOLTAGE (V) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 OUT PIN CURRENT SET PIN CURRENT REGISTER = 255 VDD AVDD tVS FIGURE 7. POWER SUPPLY SEQUENCE FIGURE 8. EXTERNAL DEBOUNCER ON CTL PIN ISL24202 CTL 0.01µF 1k Ω AVDD CLOSE TO EEPROM PROGRAM |
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