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FAN6753 データシート(PDF) 5 Page - Fairchild Semiconductor |
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FAN6753 データシート(HTML) 5 Page - Fairchild Semiconductor |
5 / 9 page AN-6755 APPLICATION NOTE © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.2 • 1/14/11 5 Figure 10 is a typical feedback circuit consisting mainly of a shunt regulator and an opto-coupler. R1 and R2 form a voltage divider for the output voltage regulation. R3 and C1 are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB= 47Ω, CFB= 1nF) placed across the FB pin and the GND can further increase the stability. The compensation network is designed around the error amplifier implemented with the shunt regulator. A certain amount of laboratory adjustment is inevitable, but in general, the type-II compensation scheme shown in Figure 10 handles most compensation requirements. There is a pole at the origin that contributes a –1 slope in the gain plot. A low-frequency zero, fEAZERO (Equation 4), flattens out the slope so the midrange gain is equal to R3/R1. A high-frequency pole, fEAPOLE (Equation 5), helps suppress any high-frequency noise from propagating through the system. R2 forms a voltage divider with R1 and provides a DC offset. By combining the Bode plots of the PWM and power stage with the error amplifier compensation, a plot of the entire system is realized. 1 3 EAZERO C R 2 1 f (4) 2 3 EAPOLE C R 2 1 f (5) The maximum sourcing current of the FB pin is 0.35mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. Thus, the value of the biasing resistor Rb is determined as: mA 35 . 0 K R V V V b Z D o (6) where: VD is the drop voltage of photodiode, approximately 1.2V; VZ is the minimum operating voltage, 2.5V of the shunt regulator; and K is the Current Transfer Rate (CTR) of the opto-coupler. For an output voltage VO=5V with CTR=100%, the maximum value of Rb is 1.2KΩ. There are some technologies to improve power saving by changing the impedance of the FB pin. This method can reduce the operating current (IDD-OP) when the feedback voltage drops below VFB-ZDC, which can further reduce IC power consumption. Figure 10 exhibits the range of the FB pin impedance change. ZFB is switched from 15K to 75K when FB is lower than VFB-ZDC. On the other hand, ZFB is switched from 75K to 15K when FB is higher than VFB-ZDCR. The change of impedance to 75K reduces the CTR, as well as the DC gain of the feedback loop. Therefore, loop stability is a critical concern. Refer to the following DC gain calculation equation: the minimum Rb value should be estimated by ZFB=75K to restrain loop instability: b FB R Z CTR Gain DC (7) where: ZFB is input impedance of FB pin. Figure 11. Power-Saving Improvement by ZFB Soft Switching The internal pull-up resistor in FAN6753 is 5kΩ, but FAN6755 has a larger pull-up resistor (15kΩ) to reduce power consumption. Therefore, Rb should be three times the original value when FAN6753 is replaced with FAN6755 to have to same loop gain. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike may occur across the sense-resistor caused by primary-side capacitance and secondary-side rectifier reverse recovery (see Figure 12). To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period (290ns), the PWM comparator is disabled and cannot switch off the gate driver. Thus, an RC filter with a small RC time constant (e.g. 100Ω + 470pF) is enough for current sensing. A non- inductive resistor for RS is recommended. Figure 12. Turn-On Spike |
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同様の説明 - FAN6753 |
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