AN-6755

APPLICATION NOTE

© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.2 • 1/14/11

5

Figure 10 is a typical feedback circuit consisting mainly of

are adjusted for control-loop compensation. A small-value

pin and the GND can further increase the stability.

The compensation network is designed around the error

amplifier implemented with the shunt regulator. A certain

amount of laboratory adjustment is inevitable, but in

general, the type-II compensation scheme shown in Figure

10 handles most compensation requirements. There is a

pole at the origin that contributes a –1 slope in the gain

any high-frequency noise from propagating through the

DC offset. By combining the Bode plots of the PWM and

power stage with the error amplifier compensation, a plot of

the entire system is realized.

1

3

EAZERO

C

R

2

1

f











(4)

2

3

EAPOLE

C

R

2

1

f











(5)

The maximum sourcing current of the FB pin is 0.35mA.

The phototransistor must be capable of sinking this current

to pull the FB level down at no load. Thus, the value of the

mA

35

.

0

K

R

V

V

V

b

Z

D

o









(6)

where:

1.2V;

regulator; and

K is the Current Transfer Rate (CTR) of the opto-coupler.

There are some technologies to improve power saving by

changing the impedance of the FB pin. This method can

power consumption. Figure 10 exhibits the range of the FB

75K

The change of impedance to 75K

 reduces the CTR, as

well as the DC gain of the feedback loop. Therefore, loop

stability is a critical concern. Refer to the following DC

b

FB

R

Z

CTR

Gain

DC





(7)

where:

Figure 11.

Soft Switching

The internal pull-up resistor in FAN6753 is 5kΩ, but

FAN6755 has a larger pull-up resistor (15kΩ) to reduce

the original value when FAN6753 is replaced with

FAN6755 to have to same loop gain.

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on

spike may occur across the sense-resistor caused by

primary-side capacitance and secondary-side rectifier

reverse recovery (see Figure 12). To avoid premature

termination of the switching pulse, a leading-edge blanking

time is built in. During this blanking period (290ns), the

PWM comparator is disabled and cannot switch off the gate

driver. Thus, an RC filter with a small RC time constant

(e.g. 100Ω + 470pF) is enough for current sensing. A non-

Figure 12.

Turn-On Spike