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FAN5355UC02X データシート(PDF) 4 Page - Fairchild Semiconductor |
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FAN5355UC02X データシート(HTML) 4 Page - Fairchild Semiconductor |
4 / 26 page © 2008 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FAN5355 • Rev. 1.0.6 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Units VCC AVIN, SW, PVIN Pins -0.3 6.5 V Other Pins -0.3 AVIN + 0.3 (6) V ESD Electrostatic Discharge Protection Level Human Body Model per JESD22-A114 3.5 KV Charged Device Model per JESD22-C101 1.5 KV TJ Junction Temperature –40 +150 °C TSTG Storage Temperature –65 +150 °C TL Lead Soldering Temperature, 10 Seconds +260 °C Note: 6. Lesser of 6.5V or AVIN+0.3V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Units VIN Supply Voltage 2.7 5.5 V f Frequency Range 2.7 3.3 MHz VCCIO SDA and SCL Voltage Swing (7) 2.5 V TA Ambient Temperature –40 +85 °C TJ Junction Temperature –40 +125 °C Note: 7. The I 2C interface operates with tHD;DAT = 0 as long as the pull-up voltage for SDA and SCL is less than 2.5V. If voltage swings greater than 2.5V are required (for example if the I 2C bus is pulled up to VIN), the minimum tHD;DAT must be increased to 80ns. Most I 2C masters change SDA near the midpoint between the falling and rising edges of SCL, which provides ample tHD;DAT . Dissipation Ratings(8) Package RθJA (9) Power Rating at TA ≤ 25°C Derating Factor > TA = 25ºC Molded Leadless Package (MLP) 49ºC/W 2050mW 21mW/ºC Wafer-Level Chip-Scale Package (WLCSP) 110ºC/W 900mW 9mW/ºC Notes: 8. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max) - TA ] / θJA. 9. This thermal data is measured with high-K board (four-layer board according to JESD51-7 JEDEC standard). |
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