データシートサーチシステム |
|
FAN5355UC03X データシート(PDF) 3 Page - Fairchild Semiconductor |
|
FAN5355UC03X データシート(HTML) 3 Page - Fairchild Semiconductor |
3 / 26 page © 2008 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FAN5355 • Rev. 1.0.6 Pin Configuration Top View Bottom View Top View Figure 2. WLCSP-12, 2.23x1.46mm Figure 3. MLP10, 3x3mm Pin Definitions Pin # Name (5) Description WLCSP MLP A1, B1 9 PGND Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The connection from this pin to the bottom of CIN should be as short as possible. A2 10 SW Switching Node. Connect to output inductor. A3 1 PVIN Power Input Voltage. Connect to input power source. The connection from this pin to CIN should be as short as possible. B2 N/A SYNC Sync. When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency on this pin. In PWM mode, when this pin is statically LOW or statically HIGH, or when its frequency is outside of the specified capture range, the regulator’s frequency is controlled by its internal 3MHz clock. B3 2 AVIN Analog Input Voltage. Connect to input power source as close as possible to the input bypass capacitor. C1 8, PAD AGND Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. C2 7 EN Enable. When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is minimized. This pin should not be left floating. C3 3 SDA SDA. I 2C interface serial data. D1 6 VOUT Output Voltage Monitor. Tie this pin to the output voltage. This is a signal input pin to the control circuit and does not carry DC current. D2 5 VSEL Voltage Select. When HIGH, VOUT is set by VSEL1. When LOW, VOUT is set by VSEL0. This behavior can be overridden through I 2C register settings. This pin should not be left floating. D3 4 SCL SCL. I 2C interface serial clock. Note: 5. All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I 2C control is unused, tie SDA and SCL to AVIN. |
同様の部品番号 - FAN5355UC03X |
|
同様の説明 - FAN5355UC03X |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |