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FAN3223C データシート(PDF) 11 Page - Fairchild Semiconductor |
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FAN3223C データシート(HTML) 11 Page - Fairchild Semiconductor |
11 / 15 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3278 • Rev. 1.0.0 11 VDD Bypass Capacitor Guidelines To enable this IC to turn a device on quickly, a local high-frequency bypass capacitor, CBYP, with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10µF to 47µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply to ≤5%. This is often achieved with a value ≥20 times the equivalent load capacitance CEQV, defined as QGATE/VDD. Ceramic capacitors of 0.1µF to 1µF or larger are common choices, as are dielectrics, such as X5R and X7R, with stable temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nF, mounted closest to the VDD and GND pins to carry the higher-frequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the CBYP can be twice as large as when a single channel is switching. Layout and Connection Guidelines The FAN3278 gate driver incorporates fast-reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 1.5A to facilitate fast voltage transition times. The following layout and connection guidelines are strongly recommended: Keep high-current output and power ground paths separate from logic and enable input signals and signal ground paths. This is especially critical when dealing with TTL-level logic thresholds at driver inputs and enable pins. Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve high- speed switching, while minimizing the loop area that can couple EMI to the driver inputs and surrounding circuitry. If the inputs to a channel are not externally connected, the internal 100k resistors indicated on block diagrams command a low output on channel A and a high output on channel B. In noisy environments, it may be necessary to tie inputs of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output mis- triggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. The turn-on and turn-off current paths should be minimized, as discussed above. Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL=PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET with a specified gate-source voltage, VGS, with gate charge, QG, at switching frequency, fSW, is determined by: PGATE=QG • VGS • fSW (2) This needs to be calculated for each P-channel and N- channel MOSFET where the QG is likely to be different. Dynamic Pre-drive / Shoot-through Current: Power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the “IDD (No- Load) vs. Frequency” graphs in Figure 9 to determine the current IDYNAMIC drawn from VDD under actual operating conditions. PDYNAMIC=IDYNAMIC • VDD (3) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming JB was determined for a similar thermal design (heat sinking and air flow): TJ =PTOTAL • JB + TB (4) where: TJ =driver junction temperature JB =(psi) thermal characterization parameter relating temperature rise to total power dissipation TB =board temperature in location defined in Note 1 under Thermal Resistance table. As an example of a power dissipation calculation, consider an application driving two MOSFETs (one P- channel and one N-channel, both with a gate charge of 60nC each) with VGS=VDD=12V. At a switching frequency of 200kHz, the total power dissipation is: PGATE=60nC • 12V • 200kHz • 2=0.288W (5) PDYNAMIC=1.65mA • 12V =0.020W (6) PTOTAL=0.308W (7) |
同様の部品番号 - FAN3223C |
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同様の説明 - FAN3223C |
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