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TDA8295 データシート(PDF) 8 Page - NXP Semiconductors

部品番号 TDA8295
部品情報  Digital global standard low IF demodulator for analog TV and FM radio
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TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
8 of 83
NXP Semiconductors
TDA8295
Digital global standard low IF demodulator for analog TV and FM radio
7.2 Pin description
31
GPIO2/SDA_O
32
GPIO1/SCL_O
33
GPIO0/VSYNC
34
VDDDR(3V3)
35
VSSDR
36
i.c.
37
IF_AGC
38
i.c.
39
VDDD(ADC)(3V3)
40
VSSA(ADC)
Table 3.
Pin allocation table …continued
Pin
Symbol
Pin
Symbol
Table 4.
Pin description
Symbol
Pin
Type[1][2]
Description
Reset
RST_N
21
I
The RST_N input is asynchronous and active LOW, and clears the TDA8295. When
RST_N goes LOW, the circuit immediately enters its Reset mode and normal operation
will resume four XIN signal falling edges later after RST_N returns HIGH. Internal
register contents are all initialized to their default values. The minimum width of RST_N
at LOW level is four XIN clock periods.
Reference
XIN
8
I
Crystal oscillator input pin. In Slave mode (typically), the XIN input simply receives a
16 MHz clock signal from an external device (typically from the TDA8275A or
TDA1827x). In Oscillator mode, a fundamental 16 MHz (typically) crystal is connected
between pin XIN and pin XOUT.
XOUT
9
O
Crystal oscillator output pin. In Slave mode, the XOUT output is not connected. In
Oscillator mode a fundamental 16 MHz (typically) crystal is connected between pin XIN
and pin XOUT.
I2C-bus
SDA
29
I/O, OD
I2C-bus bidirectional serial data. SDA is an open-drain output and therefore requires an
external pull-up resistor (typically 4.7 k
Ω).
SCL
28
I
I2C-bus clock input. SCL is nominally a square wave with a maximum frequency of
400 kHz. It is generated by the system I2C-bus master.
SADDR0
19
I
These two bits allow to select four possible I2C-bus addresses, and therefore permits to
use several TDA8295 in the same application and/or to avoid conflict with other ICs.
The complete I2C-bus address is: 1, 0, 0, SADDR1, 0, 1, SADDR0 (see also
Section 9.1).
SADDR1
20
I
I2C-bus feed-through switch or GPIO
GPIO2/SDA_O 31
I/O, OD
SDA_O is equivalent to SDA but can be 3-stated by I2C-bus programming. It is the
output of a switch controlled by I2CSW_EN parameter. SDA_O is an open-drain output
and therefore requires an external pull-up resistor (see Section 9.3.20).
GPIO1/SCL_O
32
I/O, OD
SCL_O is equivalent to SCL input but can be 3-stated by I2C-bus programming. SCL_O
is an open-drain output and therefore requires an external pull-up resistor
(see Section 9.3.20). For proper functioning of the I2C-bus feed-through, a capacitor
C = 33 pF to GND must be added (see Section 13.6).
V-sync or GPIO
GPIO0/VSYNC 33
I/O, OD
vertical synchronization pulse needed for the NXP Silicon Tuner (see Section 9.3.20)
Tuner IF AGC
IF_AGC
37
I/O, OD, T tuner IF AGC output


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