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STK672-050 データシート(PDF) 6 Page - Sanyo Semicon Device |
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STK672-050 データシート(HTML) 6 Page - Sanyo Semicon Device |
6 / 11 page STK672-040 No. 5227—6/11 2-3. RETURN (It forcibly returns the phase to the origin of current exciting phase.) 1. Pin format sCMOS Schmitt configuration containing pull-up resistor (20k Ω, typical value) 2. Noise eliminating circuit is contained. 3. Function sForces to moves to the origin of current exciting phase by setting the RETURN signal to high state. 2-4. ENABLE(ON/OFF control of exciting drive output A, A, B, and B and selection of operation/hold state in HI-IC) 1. Pin format sCMOS Schmitt configuration containing pull-up resistor (20 k Ω, typical value) 2. Function a. When the ENABLE signal is set to a high state or it is opened. It is usually placed in the operation status. b. When the ENABLE signal is set to a low state The H-IC is placed into the hold state, forcing the exciting drive output to be turned off. At this time, the system clock of the HC stops, the H-IC is not affected if the input pin other than the reset input changes. 2-5. M1, M2, and M3 (Selection of exciting modes and clock input edge timing) 1. Pin format sCMOS Schmitt configuration containing the pull-up resistor (20 k Ω typical value) 2. Functions 3. Valid timing of mode setting sThe mode must not be changed within 5 µs from the leading edge and trailing edge of the clock. M2 0 011 Phase switching clock edge timing 0 101 1 2 phase exciting 1-2 phase exciting W1-2 phase exciting 2W1-2 phase exciting Only the leading edge 0 1-2 phase exciting W1-2 phase exciting 2W1-2 phase exciting 4W1-2 phase exciting Leading edge and trailing edge M1 M3 |
同様の部品番号 - STK672-050 |
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同様の説明 - STK672-050 |
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