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33882 データシート(PDF) 10 Page - Freescale Semiconductor, Inc |
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33882 データシート(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 31 page Analog Integrated Circuit Device Data 10 Freescale Semiconductor 33882 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS SI Setup to Rising Edge (2.0 V) of SCLK (at 3.2 MHz) Required Setup Time (38) tSISU – – 45 ns SO Setup to SCLK Rising (2.0 V)/Falling (0.8 V) Edge Required Setup Time (38) tSOSU 90 – – ns SI Hold After Rising Edge (2.0 V) of SCLK (at 3.2 MHz) Required Hold Time (38) tSIHOLD – – 45 ns SO Hold After SCLK Rising (2.0 V)/Falling (0.8 V) Edge Required Hold Time (38) tSOHOLD 90 – – ns SO Rise Time CL = 200 pF tRSO – – 50 ns SO Fall Time CL = 200 pF tFSO – – 50 ns Falling Edge of CS (0.8 V) to SO Low-impedance (39) tSOEN – – 110 ns Rising Edge of CS (2.0 V) to SO High-impedance (40) tSODIS – – 110 ns Falling Edge of SCLK (0.8 V) to SO Data Valid CL = 200 pF at 3.2 MHz (41) tSOVALID – 65 80 ns CS Rising Edge to Next Falling Edge (38) Xfer DELAY – – 1.0 μs Notes 38. Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing. 39. Enable time required for SO. Pull-up resistor = 10 k Ω. 40. Disable time required for SO. Pull-up resistor = 10 k Ω. 41. Time required to obtain valid data out of SO following the falling edge of SCLK. Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125°C, unless otherwise noted. Characteristic Symbol Min Typ Max Unit |
同様の部品番号 - 33882_11 |
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同様の説明 - 33882_11 |
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