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TLE4953C データシート(PDF) 7 Page - Infineon Technologies AG |
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TLE4953C データシート(HTML) 7 Page - Infineon Technologies AG |
7 / 20 page TLE4953 TLE4953C Data Sheet 4 V 4.0, 2010-04 Figure 4 Definition of Rotation Direction Circuit Description The circuit internally is supplied by a voltage regulator. A 2 MHz on-chip oscillator serves as a clock generator for the DSP and the output encoder. Speed signal circuitry TLE4953 speed signal path comprises a pair of Hall Effect probes, separated from each other by 2.5 mm, a differential amplifier including noise limiting low-pass filter, and a comparator triggering a switched current output stage. An offset cancellation feedback loop is provided through a signal-tracking A/D converter, a digital signal processor (DSP), and an offset cancellation D/A converter. Uncalibrated Mode Occasionally a short initial offset settling time t d,input might delay the detection of the input signal. (The sensor is "blind"). During the startup phase (un-calibrated mode) the output is disabled ( I = I Low). The magnetic input signal is tracked by the speed ADC and monitored within the digital circuit. For detection the signal needs to exceed a threshold (digital noise constant d1). When the signal slope is identified as a rising edge, a trigger pulse is issued to a comparator. A second trigger pulse is issued as soon as the next rising edge is detected. Between the start-up of the magnetic input signal and the time when its second extreme is reached, the PGA (programmable gain amplifier) will switch to its appropriate position. This value is determined by the signal amplitude and initial offset value. The digital noise constant value is changing accordingly (d1 → d2, related to the corresponding PGA AEA03193 DR-L DR-R G0415 S 53C1R N S S S S S N N N N |
同様の部品番号 - TLE4953C |
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同様の説明 - TLE4953C |
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