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DAC7562SDGSR データシート(PDF) 3 Page - Texas Instruments

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部品番号 DAC7562SDGSR
部品情報  DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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DAC7562SDGSR データシート(HTML) 3 Page - Texas Instruments

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DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
www.ti.com
SLAS719C
– AUGUST 2010 – REVISED JUNE 2011
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
UNIT
AVDD to GND
–0.3 to 6
V
CLR, DIN, LDAC, SCLK and SYNC input voltage to GND
–0.3 to AVDD + 0.3
V
VOUT to GND
–0.3 to AVDD + 0.3
V
VREFIN/VREFOUT to GND
–0.3 to AVDD + 0.3
V
Operating temperature range
–40 to 125
°C
Junction temperature, maximum (TJ max)
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
DAC856x, DAC816x, DAC756x
THERMAL METRIC
DSC
DGS
UNIT
10 PINS
10 PINS
θJA
Junction-to-ambient thermal resistance(1)
62.8
173.8
°C/W
θJCtop
Junction-to-case (top) thermal resistance(2)
44.3
48.5
°C/W
θJB
Junction-to-board thermal resistance(3)
26.5
79.9
°C/W
ψJT
Junction-to-top characterization parameter(4)
0.4
1.7
°C/W
ψJB
Junction-to-board characterization parameter(5)
25.5
68.4
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance(6)
46.2
N/A
°C/W
(1)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright
© 2010–2011, Texas Instruments Incorporated
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