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STK14C88-3NF35TR データシート(PDF) 10 Page - Cypress Semiconductor |
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STK14C88-3NF35TR データシート(HTML) 10 Page - Cypress Semiconductor |
10 / 18 page STK14C88-3 Document Number: 001-50592 Rev. *D Page 10 of 18 AC Switching Characteristics SRAM Read Cycle Parameter Description 35 ns 45 ns Unit Min Max Min Max Cypress Parameter Alt tACE tELQV Chip Enable Access Time 35 45 ns tRC [9] tAVAV, tELEH Read Cycle Time 35 45 ns tAA [10] tAVQV Address Access Time 35 45 ns tDOE tGLQV Output Enable to Data Valid 15 20 ns tOHA [10] tAXQX Output Hold After Address Change 5 5 ns tLZCE [11] tELQX Chip Enable to Output Active 5 5 ns tHZCE [11] tEHQZ Chip Disable to Output Inactive 13 15 ns tLZOE [11] tGLQX Output Enable to Output Active 0 0 ns tHZOE [11] tGHQZ Output Disable to Output Inactive 13 15 ns tPU [8] tELICCH Chip Enable to Power Active 0 0 ns tPD [8] tEHICCL Chip Disable to Power Standby 35 45 ns Switching Waveforms Figure 7. SRAM Read Cycle 1: Address Controlled [9, 10] Figure 8. SRAM Read Cycle 2: CE and OE Controlled [9] Notes 9. WE and HSB must be HIGH during SRAM Read Cycles. 10. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected. 11. Measured ±200 mV from steady state output voltage. [+] Feedback [+] Feedback |
同様の部品番号 - STK14C88-3NF35TR |
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同様の説明 - STK14C88-3NF35TR |
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