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ISL29028A_1103 データシート(PDF) 4 Page - Intersil Corporation |
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ISL29028A_1103 データシート(HTML) 4 Page - Intersil Corporation |
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4 / 16 page  ISL29028A 4 FN7721.2 March 24, 2011 IIRDR_0 IRDR Sink Current PROX_DR = 0; VIRDR = 0.5V 95 110 125 mA IIRDR_1 IRDR Sink Current PROX_DR = 1; VIRDR = 0.5V 220 mA IIRDR_LEAK IRDR Leakage Current PROX_EN = 0; VDD = 3.63V (Note 10) 0.001 1 µA VIRDR Acceptable Voltage Range on IRDR Pin Register bit PROX_DR = 0 0.5 4.3 V tPULSE Net IIRDR On Time Per PROX Reading 100 µs VREF Voltage of REXT Pin 0.51 V FI2C I2C Clock Rate Range 400 kHz VI2C Supply Voltage Range for I2C Interface 1.7 3.63 V VIL SCL and SDA Input Low Voltage 0.55 V VIH SCL and SDA Input High Voltage 1.25 V ISDA SDA Current Sinking Capability VOL = 0.4V 3 5 mA IINT INT Current Sinking Capability VOL = 0.4V 3 5 mA PSRRIRDR ( ΔIIRDR)/(ΔVIRDR) PROX_DR = 0; VIRDR = 0.5V to 4.3V 4 mA/V NOTES: 7. Nonlinearity is defined as: [(Measured Counts at 53 lux)-(Expected Counts at 53 lux)]/4095. Expected counts are calculated using an endpoint linear- fit trendline from measurements at 0 lux and 90 lux. 8. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light source of the same lux level 9. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode. 10. Ability to guarantee IIRDR leakage of ~1nA is limited by test hardware. 11. For ALS applications under light-distorting glass, please see the section titled ALS Range 1 Considerations. 12. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Electrical Specifications VDD = 3.0V, TA = +25°C, REXT = 499kΩ 1% tolerance. (Continued) PARAMETER DESCRIPTION CONDITION MIN (Note 12) TYP MAX (Note 12) UNIT I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance (Note 13). PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT VI2C Supply Voltage Range for I2C Interface 1.7 3.63 V fSCL SCL Clock Frequency 400 kHz VIL SCL and SDA Input Low Voltage 0.55 V VIH SCL and SDA Input High Voltage 1.25 V Vhys Hysteresis of Schmitt Trigger Input 0.05VDD V VOL Low-level Output Voltage (Open-drain) at 4mA Sink Current 0.4 V Ii Input Leakage for each SDA, SCL pin -10 10 µA tSP Pulse Width of Spikes that must be Suppressed by the Input Filter 50 ns tAA SCL Falling Edge to SDA Output Data Valid 900 ns Ci Capacitance for each SDA and SCL pin 10 pF tHD:STA Hold Time (Repeated) START Condition After this period, the first clock pulse is generated 600 ns tLOW LOW Period of the SCL Clock Measured at the 30% of VDD crossing 1300 ns tHIGH HIGH period of the SCL Clock 600 ns tSU:STA Set-up Time for a Repeated START Condition 600 ns |
同様の部品番号 - ISL29028A_1103 |
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同様の説明 - ISL29028A_1103 |
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