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BD37A19FVM データシート(PDF) 9 Page - Rohm |
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BD37A19FVM データシート(HTML) 9 Page - Rohm |
9 / 11 page Technical Note 9/10 www.rohm.com 2010.12 - Rev.A © 2010 ROHM Co., Ltd. All rights reserved. BD37A19FVM, BD37A41FVM, BD87A28FVM, BD87A29FVM, BD87A34FVM, BD87A41FVM, BD99A41F 8) Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 9) Applications or inspection processes with modes where the potentials of the VDD pin and other pins may be reversed from their normal states may cause damage to the IC’s internal circuitry or elements. Use an output pin capacitance of 1000 µF or lower in case VDD is shorted with the GND pin while the external capacitor is charged. It is recommended to insert a diode for preventing back current flow in series with VDD or bypass diodes between Vcc and each pin. Fig.19 10) When VDD falls below the operating marginal voltage, output will be open. When output is being pulled up to input, output will be equivalent to VDD. 11) Input pin The CLK and INH pins comprise inverter gates and should not be left open. (These pins should be either pulled up or down.) Input to the CLK pin is detected using a positive edge trigger and does not affect the CLK signal duty. Input the trigger to the CLK pin within the TWH time. Bypass diode VDD Back current prevention diode Pin |
同様の部品番号 - BD37A19FVM |
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同様の説明 - BD37A19FVM |
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