Technical Note

8/25

BD37524FS

www.rohm.com

2010.03 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

●Timming Chart

CONTROL SIGNAL SPECIFICATION

(１) Electrical specifications and timing for bus lines and I/O stages

Table 1 Characteristics of the SDA and SCL bus lines for I

(Unless specified particularly, Ta=25℃, VCC=8.5V)

Parameter

Symbol

Unit

Min.

Max.

1

SCL clock frequency

ｆSCL

0

400

kHz

2

Bus free time between a STOP and START condition

tBUF

1.3

－

μS

3

Hold time (repeated) START condition. After this period, the first

clock pulse is generated

tHD;STA

0.6

－

μS

4

LOW period of the SCL clock

tLOW

1.3

－

μS

5

HIGH period of the SCL clock

tHIGH

0.6

－

μS

6

Set-up time for a repeated START condition

tSU;STA

0.6

－

μS

7

Data hold time:

tHD;DAT

0.06*

－

μS

8

Data set-up time

tSU;DAT

120

－

ns

9

Set-up time for STOP condition

tSU;STO

0.6

－

μS

All values referred to VIH min. and VIL max. Levels (see Table 2).

* A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min. of the SCL

signal) in order to bridge the undefined region of the falling edge of SCL.

About 7(tHD;DAT), 8(tSU;DAT), make it the setup which a margin is fully in .

SDA

S

SCL

P

Sr

P