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GS4910BCNE3 データシート(PDF) 10 Page - Gennum Corporation

部品番号 GS4910BCNE3
部品情報  HD/SD/Graphics Clock and Timing Generator with GENLOCK
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メーカー  GENNUM [Gennum Corporation]
ホームページ  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS4910BCNE3 データシート(HTML) 10 Page - Gennum Corporation

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GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
10 of 119
1.3 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
1LOCK_LOSTNon
Synchronous
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be HIGH if the output is not genlocked to the input.
The GS4911B/GS4910B monitors the output pixel/line counters, as
well as the internal lock status from the genlock block and asserts
LOCK_LOST HIGH if it is determined that the output is not
genlocked to the input. This pin will be LOW if the device
successfully genlocks the output clock and timing signals to the
input reference.
If LOCK_LOST is LOW, the reference timing generator outputs will
be phase locked to the detected reference signal, producing an
output in accordance with the video standard selected by the
VID_STD[5:0] pins.
2REF_LOSTNon
Synchronous
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be HIGH if:
• No input reference signal is applied to the device; or
• The input reference applied does not meet the
minimum/maximum timing requirements described in
Section 3.5.2 on page 46.
This pin will be LOW otherwise.
If the reference signal is removed when the device is in Genlock
mode, REF_LOST will go HIGH and the GS4911B/GS4910B will enter
Freeze mode (see Section 3.2.1.2 on page 41).
3
VID_PLL_VDD
Power
Supply
Most positive power supply connection for the video clock synthesis
internal block. Connect to +1.8V DC.
4
VID_PLL_GND
Power
Supply
Ground connection for the video clock synthesis internal block.
Connect to GND.
5
XTAL_VDD
Power
Supply
Most positive power supply connection for the crystal buffer.
Connect to either +1.8V DC or +3.3V DC.
NOTE: Connect to +3.3V for minimum output PCLK jitter.
6
X1
Non
Synchronous
Input
ANALOG SIGNAL INPUT
Connect to a 27MHz crystal or a 27MHz external clock source. See
Figure 1-1.
7X2
Non
Synchronous
Output
ANALOG SIGNAL OUTPUT
Connect to a 27MHz crystal, or leave this pin open circuit if an
external clock source is applied to pin 6. See Figure 1-1.
8XTAL_GND
Power
Supply
Ground connection for the crystal buffer. Connect to GND.


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