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FM24V10-G データシート(PDF) 2 Page - Ramtron International Corporation |
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FM24V10-G データシート(HTML) 2 Page - Ramtron International Corporation |
2 / 16 page FM24V10 - 1Mb I2C FRAM Rev. 2.0 May 2010 Page 2 of 16 Address Latch 16K x 64 FRAM Array Data Latch 8 SDA Counter Serial to Parallel Converter Control Logic SCL WP A1, A2 Device ID and Serial Number 8 Figure 1. FM24V10 Block Diagram Pin Description Pin Name Type Pin Description A1, A2 Input Device Select Address 1, 2: These pins are used to select one of up to 4 devices of the same type on the same two-wire bus. To select the device, the address value on the two pins must match the corresponding bits contained in the slave address. The address pins are pulled down internally. SDA I/O Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is open-drain and is intended to be wire-OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor is required. SCL Input Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of the part on the falling edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. WP Input Write Protect: When tied to VDD, addresses in the entire memory map will be write- protected. When WP is connected to ground, all addresses may be written. This pin is pulled down internally. VDD Supply Supply Voltage VSS Supply Ground |
同様の部品番号 - FM24V10-G |
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同様の説明 - FM24V10-G |
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