LC88F83B0A

No.A1228-4/25

Interrupts

• 12 sources, 11 vector addresses

1) Provides three levels of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the

current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level

takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector

address takes precedence.

No.

Vector Address

Interrupt Source

1

08000H

WATCHDOGTIMER

2

08004H

BASETIMER

3

08008H

TIMER0

4

08018H

SIO0

5

0801CH

TIMER1

6

08020H

UART2

7

08024H

TIMER3

8

08028H

TIMER4

9

0802CH

TIMER5

10

08030H

ADC

11

0803CH

P00 to P05

SEG71 to SEG64

• The priority level can be specified by three levels.

• Of interrupts of the same level, the one with the smallest vector address takes precedence.

Subroutine Stack Levels

• Max- whole RAM area (Stack is set in RAM)

Oscillation Circuits

• OSC1: For system clock

ceramic oscillation with external CGC, CDC or RC oscillation (external RCR1)

• OSC0: For low-speed system clock, base timer count, for LCD display

32kHz crystal oscillation with external CGX, CDX or RC oscillation (external RCR0)

• Internal oscillation circuit: Internal RC

* Depends on control resister for each oscillator operation and stop.

Initial setting - External oscillation stop, internal RC oscillation operation