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SIP11203 データシート(PDF) 10 Page - Vishay Siliconix |
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SIP11203 データシート(HTML) 10 Page - Vishay Siliconix |
10 / 18 page www.vishay.com 10 Document Number: 73868 S11-0975–Rev. C, 16-May-11 Vishay Siliconix SiP11203, SiP11204 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 NORMAL DRIVER OPERATION In normal operation, OUTA responds to INA, and OUTB to INB. The signal path from input to output is non-inverting. The output drivers have high and deliberately asymmetrical current sink and source capabilities (4 A ISINK, 2.2 A ISOURCE). The high currents allow driving large synchronous rectifiers at the switching frequencies found in modern power converters. At the same time, the driver asymmetry enforces a rapid turn-off of the rectifier MOSFETs relative to their turn-on, to avoid rectifier crossconduction, and the low driver impedances to PGND help ensure that the rectifier MOSFETs do not exhibit unwanted turn-on during converter operation. As with most logic circuits, OUTA and OUTB do not exhibit indeterminate output states even the transitions at INA and INB are excessively slow. The solid and sharp driving signals from OUTA and OUTB will ensure the proper function of the rectifier MOSFETs in the final application circuit. POWER-DOWN DRIVER OPERATION If the timing pulses from the primary of the DC-DC converter cease, the SiP11203/SiP11204 must assume that the power to the primary of the DC-DC converter has failed. Upon detecting this condition, the part must put the main synchronous rectifier drivers into a “safe” condition, and simultaneously ensure that the rectifier MOSFETs are turned off. A unique feature of the SiP11203/SiP11204 is their ability to turn off the synchronous rectifiers via a controlled excursion through their linear region. This can help to prevent output ringing at turn-off. A missing-pulses detector is provided on the IC to initiate the soft power down. This detector, which is enabled once the VREF pin has reached 1.1 V, continually monitors INA and INB for lack of switching activity. An external resistor from RPD to ground defines a current out of CPD (I = 2.5 V/RPD), which is used to charge an external capacitor from CPD to ground. The voltage on CPD is internally compared to the 2.5 V developed by VREFINT. Whenever either input goes low, the voltage at CPD is reset to 0 V. However, if both inputs are high for a period of RPD × CPD, the voltage at CPD will exceed the 2.5 V comparison threshold, and the power-down latch will be set (See Figure 6). • The VREF pin bypass capacitor is discharged towards 0 V, to ensure an orderly soft-start cycle when operation resumes, • The main drivers are forced into a high-impedance state, • Internal pull-downs (current sinks) from the OUTA and OUTB pins to ground are enabled, • The pull-down currents on OUTA and OUTB are set by RPD, to allow a “soft” turn-off of the synchronous rectifiers. Figure 4. Soft-start parameters of the SiP11203/SiP11204 are programmable with external components V VL VREF 0.9* V L 3.55 V time 1.225 V 5 V Internal logic circuits enabled VREF released to rise Rate of rise determined by external VREF capacitor Rate of rise determined by external VL capacitor 2.5 V VREFINT Enabled by CUVLO R |
同様の部品番号 - SIP11203 |
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同様の説明 - SIP11203 |
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