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74FCT388915T150J データシート(PDF) 2 Page - Integrated Device Technology

部品番号 74FCT388915T150J
部品情報  3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

74FCT388915T150J データシート(HTML) 2 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
2
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
PIN CONFIGURATION
PIN DESCRIPTION
Q/2
GND
Q3
VCC
Q2
GND
LOCK
FEEDBK
REF_SEL
SYNC(0)
VCC(AN)
LF
GND(AN)
SYNC(1)
28
43
21
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5
6
7
8
9
10
VCC
OE/RST
FEEDBACK
1
2
3
4
20
19
18
17
16
15
14
13
Q4
12
11
GND
Q/2
REF_SEL
SYNC(0)
VCC(AN)
LF
VCC
GND
Q3
VCC
Q2
GND
GND(AN)
LOCK
Q5
2Q
21
22
23
24
SYNC(1)
FREQ_SEL
GND
Q0
VCC
Q1
GND
PLL_EN
25
26
27
28
SSOP
TOP VIEW
PLCC
TOP VIEW
Pin Name
I/O
Description
SYNC(0)
I
Referenceclockinput
SYNC(1)
I
Referenceclockinput
REF_SEL
I
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
FREQ_SEL
I
Selects between ÷ 1 and ÷ 2 frequency options (refer to functional block diagram)
FEEDBACK
I
Feedbackinputtophasedetector
LF
I
Input for external loop filter connection
Q0-Q4
O
Clock output
Q5
O
Inverted clock output
2Q
O
Clock output (2 x Q frequency)
Q/2
O
Clock output (Q frequency ÷ 2)
LOCK
O
Indicates phase lock has been achieved (HIGH when locked)
OE/
RST
I
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in
HIGH impedance.
PLL_EN
I
Disables phase-lock for low frequency testing (refer to functional block diagram)


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