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74FCT388915T15PY データシート(PDF) 7 Page - Integrated Device Technology

部品番号 74FCT388915T15PY
部品情報  3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

74FCT388915T15PY データシート(HTML) 7 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
7
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1,
Q2, Q3 and Q4).
1:2 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
Inthisapplication,theQ/2outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4,
Q5) will
always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2
frequency.
1:1 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
Inthisapplication,theQ4outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The
Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run
at 2X the Q frequency.
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
2:1 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
Inthisapplication,the2QoutputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q
frequency will equal the SYNC frequency. The Q/2 output will always run at
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Figure 3a. Wiring Diagram and Frequency Relationships With Q/
2 Output Feedback
Figure 3c. Wiring Diagram and Frequency Relationships With
2Q Output Feedback
Figure 3b. Wiring Diagram and Frequency Relationships With
Q4 Output Feedback
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEED BAC K
REF_SEL
SYNC(0)
VCC(AN)
GN D(AN)
Q4
Q5
2Q
LOW
50 M Hz signal
12.5 M Hz feedback signal
HIGH
HIGH
HIGH
25 MHz
"Q"
C lock
Outputs
12.5 MHz
input
LF
FC T388915T
RST
OE/
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEED BAC K
REF_SEL
SYNC (0)
VCC(AN)
GN D(AN )
Q4
Q5
2Q
LOW
50 M H z signal
25 M Hz feedback signal
HIGH
HIGH
HIGH
25 M Hz
"Q"
C lock
O utputs
25 M H z
input
12.5 M Hz
signal
LF
FC T388915T
RST
OE/
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEED BACK
REF_SEL
SYNC(0)
VCC(AN)
GND(AN)
Q4
Q5
2Q
LOW
50 M Hz feedback signal
HIGH
HIGH
HIGH
25 M Hz
"Q"
Clock
Outputs
50 M Hz
input
12.5 MHz
input
LF
FCT388915T
RST
OE/


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