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932S208YFLNT データシート(PDF) 2 Page - Integrated Device Technology |
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932S208YFLNT データシート(HTML) 2 Page - Integrated Device Technology |
2 / 21 page IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor 2 Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 REF0 OUT 14.318 MHz reference clock. 2 REF1 OUT 14.318 MHz reference clock. 3 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 4X1 IN Crystal input, Nominally 14.318MHz. 5 X2 OUT Crystal output, Nominally 14.318MHz 6 GND PWR Ground pin. 7 PCICLK_F0 OUT Free running PCI clock not affected by PCI_STOP# . 8 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# . 9 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP# . 10 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 11 GND PWR Ground pin. 12 PCICLK0 OUT PCI clock output. 13 PCICLK1 OUT PCI clock output. 14 PCICLK2 OUT PCI clock output. 15 PCICLK3 OUT PCI clock output. 16 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 17 GND PWR Ground pin. 18 PCICLK4 OUT PCI clock output. 19 PCICLK5 OUT PCI clock output. 20 PCICLK6 OUT PCI clock output. 21 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Internal pull-up of 150K nominal. 22 3V66_0 OUT 3.3V 66.66MHz clock output 23 3V66_1 OUT 3.3V 66.66MHz clock output 24 VDD3V66 PWR Power pin for the 3V66 clocks. 25 GND PWR Ground pin. 26 3V66_2 OUT 3.3V 66.66MHz clock output 27 3V66_3 OUT 3.3V 66.66MHz clock output 28 SCLK IN Clock pin of I2C circuitry 5V tolerant |
同様の部品番号 - 932S208YFLNT |
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同様の説明 - 932S208YFLNT |
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