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932S805CGLFT データシート(PDF) 7 Page - Integrated Device Technology

部品番号 932S805CGLFT
部品情報  K8 Clock Chip for Serverworks HT2100 Servers
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

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ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
7
IDT®
K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
SMBus Table: Frequency Select and Spread Control Register
Pin #
Name
Control Function
Type0
1PWD
Bit 7
FS Source
Latched Input or SMBus Frequency
Select
RW Latched Inputs
SMBus
0
Bit 6
Spread
Spectrum
Enable
Spread Enable for CPU, SRC and PCI Outputs.
Setting SPREAD_EN pin to '1', forces
Spread ON and overides this bit.
RW
OFF
ON
0
Bit 5
Reserved
Reserved
RW
Reserved
Reserved
0
Bit 4
Reserved
Reserved
RW
Reserved
Reserved
0
Bit 3
FS3
Freq Select Bit 3
RW
Latched
Bit 2
FS2
Freq Select Bit 2
RW
Latched
Bit 1
FS1
Freq Select Bit 1
RW
Latched
Bit 0
FS0
Freq Select Bit 0
RW
Latched
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1PWD
Bit 7
REF2
Output Enable
RW
Disable (Low)
Enable
1
Bit 6
REF1
Output Enable
RW
Disable (Low)
Enable
1
Bit 5
REF0
Output Enable
RW
Disable (Low)
Enable
1
Bit 4
PCICLK1
Output Enable
RW
Disable (Low)
Enable
1
Bit 3
PCICLK0
Output Enable
RW
Disable (Low)
Enable
1
Bit 2
48MHz_2
Output Enable
RW
Disable (Low)
Enable
1
Bit 1
48MHz_1
Output Enable
RW
Disable (Low)
Enable
1
Bit 0
48MHz_0
Output Enable
RW
Disable (Low)
Enable
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1PWD
Bit 7
Reserved
Reserved
RW
Reserved
Reserved
0
Bit 6
CPUCLK8(6)
RW
Disable
Enable
1
Bit 5
CPUCLK8(5)
RW
Disable
Enable
1
Bit 4
CPUCLK8(4)
RW
Disable
Enable
1
Bit 3
CPUCLK8(3)
RW
Disable
Enable
1
Bit 2
CPUCLK8(2)
RW
Disable
Enable
1
Bit 1
CPUCLK8(1)
RW
Disable
Enable
1
Bit 0
CPUCLK8(0)
RW
Disable
Enable
1
-
-
-
-
-
4
6
Byte 1
5
17
10
9
16
11
Byte 2
-
47/46
45/44
59/58
57/56
53/52
51/50
43/42
Byte 0
-
-
-
Output Enable
When Disabled
CPUCLKT = 0
CPUCLKC = 1
See CPU Frequency Select
Table


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