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74AUP1G07GS データシート(PDF) 9 Page - NXP Semiconductors |
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74AUP1G07GS データシート(HTML) 9 Page - NXP Semiconductors |
9 / 18 page 74AUP1G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 15 November 2011 9 of 18 NXP Semiconductors 74AUP1G07 Low-power buffer with open-drain output [1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M. Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times 001aac521 DUT RT VI VO VEXT VCC RL 5 k Ω CL G Table 10. Test data Supply voltage Load VEXT VCC CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2 V CC |
同様の部品番号 - 74AUP1G07GS |
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同様の説明 - 74AUP1G07GS |
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