Si52144

8

Preliminary Rev. 0.1

Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.



CL: Crystal load capacitance



CLe: Actual loading seen by crystal using standard value trim capacitors



Ce: External trim capacitors



Cs: Stray capacitance (terraced)



Ci: Internal capacitance (lead frame, bond wires, etc.)

2.2. OE Clarification

The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE

to be driven at all time and even though it has an internally 100 k

 resistor.

2.3. OE Assertion

The OE signals are active high input used for synchronous stopping and starting the DIFF output clocks respectively

while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high

causes stopped respective DIFF output to resume normal operation. No short or stretched clock pulses are produced

when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output

clock cycles.

2.4. OE Deassertion

When the OE pin is deasserted by making its logic low, the corresponding DIFF output is stopped cleanly, and the

final output state is driven low.

2.5. SSON Clarification

SSON is an active input used to enable –0.5% spread on all DIFF outputs. When sampled high, –0.5% spread is

enabled on all DIFF outputs. When sampled low, the DIFF output frequencies are non-spread.

Load Capacitance (each side)

Total Capacitance (as seen by the crystal)

Ce = 2 x CL – (Cs + Ci)

Ce1 + Cs1 + Ci1

1

+

Ce2 + Cs2 + Ci2

1

()

1

=

CLe