AD6657A datasheet(7/36 Pages) AD

部品番号	AD6657A

部品情報	Quad IF Receiver

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Data Sheet

AD6657A

Rev. 0 | Page 7 of 36

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless

otherwise noted.

Table 3.

Parameter

Temperature

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

0.9

V

Differential Input Voltage

Full

0.2

3.6

V p-p

Input Voltage Range

Full

AGND − 0.3

AVDD + 0.2

V

High Level Input Voltage

Full

1.2

2.0

V

Low Level Input Voltage

Full

0

0.8

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

−10

+10

µA

Input Resistance

Full

8

10

12

kΩ

Input Capacitance

Full

4

pF

SYNC INPUT

Logic Compliance

CMOS

Internal Bias

Full

0.9

V

Input Voltage Range

Full

AGND

AVDD

V

High Level Input Voltage

Full

1.2

AVDD

V

Low Level Input Voltage

Full

AGND

0.6

V

High Level Input Current

Full

−100

+100

µA

Low Level Input Current

Full

−100

+100

µA

Input Resistance

Full

12

16

20

kΩ

Input Capacitance

Full

1

pF

LOGIC INPUT (CSB)1

High Level Input Voltage

Full

1.22

2.1

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

40

132

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUT (SCLK)2

High Level Input Voltage

Full

1.22

2.1

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−92

−135

µA

Low Level Input Current

Full

−10

+10

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUT/OUTPUT (SDIO)2

High Level Input Voltage

Full

1.22

2.1

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

38

128

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

5

pF

同様の部品番号 - AD6657A

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