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ADUM3223BRZ データシート(PDF) 4 Page - Analog Devices |
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ADUM3223BRZ データシート(HTML) 4 Page - Analog Devices |
4 / 20 page ADuM3223/ADuM4223 Data Sheet Rev. 0| Page 4 of 20 ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 12 V. Switching specifications are tested with CMOS signal levels. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, Quiescent IDDI(Q) 0.87 1.4 mA Output Supply Current, Per Channel, Quiescent IDDO(Q) 2.3 3.2 mA Supply Current at 1 MHz VDD1 Supply Current IDD1(Q) 1.1 1.5 mA Up to 1 MHz, no load VDDA/VDDB Supply Current IDDA/IDDB(Q) 5.6 8.0 mA Up to 1 MHz, no load Input Currents IIA, IIB −10 +0.01 +10 µA 0 ≤ VIA, VIB ≤ VDD1 Logic High Input Threshold VIH 0.7 × VDD1 V Logic Low Input Threshold VIL 0.3 × VDD1 V Logic High Output Voltages VOAH, VOBH VDD2 – 0.1 VDD2 V IOx = −20 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.15 V IOx = +20 mA, VIx = VIxL Undervoltage Lockout, VDD2 Supply Positive Going Threshold VDD2UV+ 4.1 4.4 V A-grade Negative Going Threshold VDD2UV− 3.2 3.6 V A-grade Hysteresis VDD2UVH 0.5 V A-grade Positive Going Threshold VDD2UV+ 6.9 7.4 V B-grade Negative Going Threshold VDD2UV− 5.7 6.2 V B-grade Hysteresis VDD2UVH 0.7 V B-grade Positive Going Threshold VDD2UV+ 10.5 11.1 V C-grade Negative Going Threshold VDD2UV− 8.9 9.6 V C-grade Hysteresis VDD2UVH 0.9 V C-grade Output Short-Circuit Pulsed Current1 IOA(SC), IOB(SC) 2.0 4.0 A VDD2 = 12 V Output Pulsed Source Resistance ROA, ROB 1.1 Ω VDD2 = 12 V Output Pulsed Sink Resistance ROA, ROB 0.6 Ω VDD2 = 12 V SWITCHING SPECIFICATIONS Pulse Width2 PW 50 ns CL= 2 nF, VDD2 = 12 V Maximum Data Rate3 1 MHz CL= 2 nF, VDD2 = 12 V Propagation Delay4 tDHL, tDLH 30 42 54 ns CL= 2 nF, VDD2 = 12 V, see Figure 20 ADuM3223A/ADuM4223A tDHL, tDLH 32 46 60 ns CL= 2 nF, VDD2 = 4.5 V, see Figure 20 Propagation Delay Skew5 tPSK 12 ns CL= 2 nF, VDD2 = 12 V, see Figure 20 Channel-to-Channel Matching6 tPSKCD 1 5 ns CL= 2 nF, VDD2 = 12 V, see Figure 20 tPSKCD 1 7 ns CL= 2 nF, VDD2 = 4.5 V, see Figure 20 Output Rise/Fall Time (10% to 90%) tR/tF 6 12 22 ns CL= 2 nF, VDD2 = 12 V, see Figure 20 Dynamic Input Supply Current Per Channel IDDI(D) 0.05 mA/Mbps VDD2 = 12 V Dynamic Output Supply Current Per Channel IDDO(D) 1.65 mA/Mbps VDD2 = 12 V Refresh Rate fr 1.1 Mbps 1 Short-circuit duration less than 1 µs. Average power must conform to the limit shown under the Absolute Maximum Ratings. 2 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 4 t DLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay parameters. 5 t PSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels. |
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同様の説明 - ADUM3223BRZ |
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