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SLA24C01-D データシート(PDF) 7 Page - Siemens Semiconductor Group |
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SLA24C01-D データシート(HTML) 7 Page - Siemens Semiconductor Group |
7 / 27 page SLx 24C01/02/P Semiconductor Group 7 1998-07-27 3 I 2C-Bus Characteristics The SLx 24C01/02/P devices support a master/slave bidirectional bus oriented protocol in which the EEPROM always takes the role of a slave. Figure 3 Bus Configuration Master Device that initiates the transfer of data and provides the clock for both transmit and receive operations. Slave Device addressed by the master, capable of receiving and transmitting data. Transmitter The device with the SDA as output is defined as the transmitter. Due to the open drain characteristic of the SDA output the device applying a low level wins. Receiver The device with the SDA as input is defined as the receiver. Slave 1 Slave 2 Slave 3 Slave 4 Slave 8 Slave 5 Slave 6 Slave 7 Master VCC CC V IES02183 SCL SDA |
同様の部品番号 - SLA24C01-D |
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同様の説明 - SLA24C01-D |
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