CDCM6208V2RGZR datasheet(8/78 Pages) TI

部品番号	CDCM6208V2RGZR

部品情報	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

MAX

UNITS

Supply Voltage Range, VDD_PRI, VDD_SEC, VDD_Yx_Yy, VDD_PLL[2:1], DVDD

-0.5

4.6

V

4.6

Input Voltage Range CMOS control inputs, VIN

-0.5

AND

V

V DVDD+ 0.5

4.6

Input Voltage Range PRI/SEC inputs

AND

V

VVDDPRI.SEC+ 0.5

Output Voltage Range, VOUT

-0.5

VYxYy+ 0.5

V

Input Current, IIN

20

mA

Output Current, IOUT

50

mA

Storage Temperature Range, TSTG

-65

150

°C

Junction Temperature, TJ

125

°C

Electrostatic Discharge (HBM), ESD

2

kV

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute—maximum—rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNITS

VDD_Yx_Y

Output Supply Voltage

1.71

1.8/2.5/3.3

3.465

V

y

VDD_PLL1

Core Analog Supply Voltage

1.71

1.8/2.5/3.3

3.465

V

VDD_PLL2

DVDD

Core Digital Supply Voltage

1.71

1.8/2.5/3.3

3.465

V

VDD_PRI,

Reference Input Supply Voltage

1.71

1.8/2.5/3.3

3.465

V

VDD_SEC

VDD power-up ramp time (0 to 3.3 V) PDN left open, all VDD tight

ΔVDD/Δt

50 < tPDN

ms

together PDN low-high is delayed (1)

TA

Ambient Temperature

-40

85

°C

SDA and SCL in I2C Mode (SI_MODE[1:0] = 01)

DVDD = 1.8 V

-0.5

2.45

V

VI

Input Voltage

DVDD = 3.3 V

- 0.5

3.965

V

100

dR

Data Rate

kbps

400

0.7 x

VIH

High-level input voltage

V

DVDD

0.3 x

VIL

Low-level input voltage

V

DVDD

CBUS_I2C

Total capacitive load for each bus line

400

pF

(1)

For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating.

For slower power up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD,

VDD_PLLx, and VDD_PRI/SEC reach at least 1.45V supply voltage. See application section on mixing power supplies and particularly

Figure 32 for details.

8

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