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CDCUN1208LPRHBR データシート(PDF) 8 Page - Texas Instruments

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部品番号 CDCUN1208LPRHBR
部品情報  400 MHz Low Power 2:8 Fan-Out Buffer
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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CDCUN1208LPRHBR データシート(HTML) 8 Page - Texas Instruments

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CDCUN1208LP
SCAS928 – MAY 2012
www.ti.com
CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = HCSL)
Unless otherwise noted, VDDOx = 1.8V, 2.5V, 3.3V; TA = –40°C to 85°C. See Figure 12, Figure 13, and Figure 14.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOUT
Output frequency
0.008
400
MHz
Vmax
Absolute maximum output voltage(1)
See Figure 3
1.15
V
Vmin
Absolute minimum output voltage(2)
See Figure 3
–0.3
V
RL = single ended to GND = 50 Ω, CL = 2pF,
600
VDDOx = 2.5V, 3.3V See Figure 12
Single ended output voltage –
VOH
mV
high(3)
RL = single ended to GND = 50 Ω, CL = 2pF,
550
VDDOx = 1.8V See Figure 12
RL = single ended to GND = 50 Ω, CL = 2pF,
VOL
Single ended output voltage – low(3)
150
mV
See Figure 12
VCROSS
Output crossing point voltage(3)
See Figure 3
250
550
mV
VCROSSΔ
VCROSS Total variation
(3)
See Figure 4
140
mV
VRB
Ring back voltage margin(3)
See Figure 5
–100
100
mV
TSTABLE
Time before VRB is Allowed
(3),(4)
See Figure 5
500
ps
VIN, DIFF, PP = 0.9V, RL = single ended to GND = 50 Ω,
VOS
Output AC common mode
75
125
mVP-P
2 pF
fOUT = 100 MHz, 10k-20M integration bandwidth.
TjitHCSL
Additive jitter, input set to HCSL(5)
380
fs, rms
Differential Measurement
fOUT = 100 MHz, 10k-20M integration bandwidth.
TjitLVDS
Additive jitter, input set to LVDS(5)
280
fs, rms
Differential Measurement
Slow, +150mV differential, See Figure 6, VDDOx = 3.3V
300
Slow, +150mV differential, See Figure 6, VDDOx = 1.8V
230
tR/tF
Output rise/fall time(6)
Med., +150mV differential, See Figure 6, VDDOx = 3.3V
240
ps
Med., +150mV differential, See Figure 6, VDDOx = 1.8V
180
Fast, +150mV differential, See Figure 6
140
TMRF
Output rise/fall time matching
See Figure 7
20%
ODC
Output duty cycle(7)
Differential Measurement, See Figure 8
45%
55%
ERC set to high rate. Input tr, tf > 0.6 V/ns, VDD = 2.5V,
3.8
3.3V
TDLYO
Propagation delay
ns
ERC set to high rate. Input tr, tf > 0.6 V/ns, VDD = 1.8V
4.3
tSKEW
Skew between outputs(8)
Differential Measurement, Input tr, tf > 0.6 V/ns
35
50
ps
Pin mode, fout = 100 MHz, device in active mode with
tOE
Output enable to stable clock output
2
µs
outputs disabled, OE asserted
PD de-asserted to stable clock
Host mode, fout = 100 MHz, device in power down
tPD
15
µs
output
mode, PD de-asserted
Time from power applied to stable
Pin mode, fout = 100 MHz, OE asserted, measured
tPU
1
ms
clock output(9)
from time VDD is valid to stable output
(1)
Single-ended measurement includes overshoot. Measurement is taken at load capacitors CL (see Figure 12).
(2)
Single-ended measurement, includes undershoot Measurement is taken at load capacitors CL (see Figure 12 ).
(3)
Measurement is taken at load capacitors CL (see Figure 12). If VDDOx = 1.8V, the specified minimum VOH is 550 mV.
(4)
TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is
allowed to droop back into the VRB ±100 mV differential range. See Figure 5.
(5)
tRfin = tFfin ≥ 0.6 V/ns.
(6)
Measured from –150 mV to +150 mV on the differential waveform. The signal must be monotonic through the measurement region for
rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. Slow is 0.53V/ns, medium is 1.05V/ns,
and fast is 2.1V/ns. The PCIe CEM spec. has a window of 0.6V/ns to 4V/ns.
(7)
Assumes input duty cycle = 50%.
(8)
Skew measured between identical output types with identical loads, identical output power supplies, and identical edge rate settings.
(9)
Parameter depends significantly on power supply design and supply voltage rise time.
8
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