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データシートサーチシステム |
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データシートサーチシステム |
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SL4516BD データシート(PDF) 4 Page - System Logic Semiconductor |
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SL4516BD データシート(HTML) 4 Page - System Logic Semiconductor |
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4 / 6 page  SL4516B System Logic Semiconductor SLS AC ELECTRICAL CHARACTERISTICS(C L=50pF, RL=200k Ω, Input t r=tf=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25 °C ≤125°C Unit tPHL, tPLH Maximum Propagation Delay, Clock to Q (Figure 1) 5.0 10 15 400 200 150 400 200 150 800 400 300 ns tPHL, tPLH Maximum Propagation Delay, Preset or Reset to Q (Figure 1) 5.0 10 15 420 210 160 420 210 160 840 420 320 ns tPHL, tPLH Maximum Propagation Delay, Clock to Carry Out (Figure 1) 5.0 10 15 480 240 180 480 240 180 960 480 360 ns tPHL, tPLH Maximum Propagation Delay, Carry In to Carry Out (Figure 1) 5.0 10 15 250 120 100 250 120 100 500 240 200 ns tPHL, tPLH Maximum Propagation Delay, Preset or Reset to Carry Out (Figure 1) 5.0 10 15 640 320 250 640 320 250 1280 640 500 ns tTHL, tTLH Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns CIN Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS(C L=50pF, RL=200 k Ω, Input t r=tf=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25 °C ≤125°C Unit tsu Minimum Setup Time, P to Preset Enable (Figure 1) 5.0 10 15 25 10 10 25 10 10 50 20 20 ns tsu Minimum Setup Time, Up/Down to Clock (Figure 1) 5.0 10 15 ns tsu Minimum Setup Time, Carry In to Clock (Figure 1) 5.0 10 15 ns th Minimum Hold Time, Clock to Carry In (Figure 1) 5.0 10 15 60 30 30 60 30 30 120 60 60 ns th Minimum Hold Time, Clock to Up/Down (Figure 1) 5.0 10 15 30 30 30 30 30 30 60 60 60 ns th Minimum Hold Time, Preset enable to P (Figure 1) 5.0 10 15 70 40 40 70 40 40 140 80 80 ns |
同様の部品番号 - SL4516BD |
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同様の説明 - SL4516BD |
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