データシートサーチシステム |
|
DAC715P データシート(PDF) 7 Page - Texas Instruments |
|
DAC715P データシート(HTML) 7 Page - Texas Instruments |
7 / 14 page 7 ® DAC715 D15 MSB 16-Bit Input Latch 16-Bit D/A Latch 28 27 26 25 24 23 22 21 20 19 18 17 D0 LSB 6 5 +10V Reference 2 1 7 DCOM +V CC ACOM V REF OUT Gain Adjust 10 WR 12 A 0 11 A 1 9 CLR 8 – V CC 16 15 14 13 Offset Adjust 4 3 V OUT D/A Switches –V CC +2.5V 15k Ω 170 Ω 10k Ω 5k Ω Offset Adjustment Apply the digital input code that produces zero output voltage and adjust the offset potentiometer or the offset adjust D/A converter for 0V. FIGURE 3. Relationship of Offset and Gain Adjustments. GAIN AND OFFSET ADJUSTMENTS Figure 3 illustrates the relationship of offset and gain adjust- ments for a unipolar connected D/A converter. Offset should be adjusted first to avoid interaction of adjustments. See Table I for calibration values and codes. These adjustments have a minimum range of ±0.3%. FIGURE 2. Equivalent Circuit of Digital Inputs. FIGURE 1. DAC715 Block Diagram. R R = 1k Ω: A 0, A1, WR, CLR 3k Ω: D0...D15 ESD Protection Circuit 6.8V 5pF Digital Input –V CC +V CC Range of Offset Adjust Offset Adj. Translates the Line Digital Input 7FFF H 0000 H 8000 H Full Scale Range Gain Adjust Rotates the Line Zero Range of Gain Adjust ≈ ±0.3% ≈ ±0.3% + Full Scale |
同様の部品番号 - DAC715P |
|
同様の説明 - DAC715P |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |