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SL74HC166N データシート(PDF) 4 Page - System Logic Semiconductor |
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SL74HC166N データシート(HTML) 4 Page - System Logic Semiconductor |
4 / 6 page SL74HC166 System Logic Semiconductor SLS AC ELECTRICAL CHARACTERISTICS(C L=50pF,Input t r=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55 °C ≤85°C ≤125°C Unit fmax Minimum Clock Frequency (50% Duty Cycle) (Figures 2 and 4) 2.0 4.5 6.0 6.0 31 36 5.0 25 28 4.2 21 25 MHz tPLH, tPHL Maximum Propagation Delay, Clock (or Clock Inhibit) to QH (Figures 2,3 and 4) 2.0 4.5 6.0 140 28 24 175 35 30 210 42 36 ns tPHL Maximum Propagation Delay , Clear to QH (Figures 1 and 4) 2.0 4.5 6.0 150 30 26 200 40 34 230 48 40 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 75 16 14 95 20 18 110 25 20 ns CIN Maximum Input Capacitance - 10 10 10 pF Power Dissipation Capacitance (Per Package) Typical @25 °C,V CC=5.0 V CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC 2f+I CCVCC 140 pF TIMING REQUIREMENTS(C L=50pF,Input t r=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55 °C ≤85°C ≤125°C Unit tsu Minimum Setup Time, Shift/Load to Clock (Figure 3) 2.0 4.5 6.0 80 16 14 100 20 18 120 24 20 ns tsu Minimum Setup Time, Data before Clock (or Clock Inhibit) (Figure 3) 2.0 4.5 6.0 80 16 14 100 20 18 120 24 20 ns tw Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns |
同様の部品番号 - SL74HC166N |
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同様の説明 - SL74HC166N |
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