SL74HC174D datasheet(4/5 Pages) SLS

部品番号	SL74HC174D

部品情報	Hex D Flip-Flop with Common Clock and Reset

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メーカー	SLS [System Logic Semiconductor]

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SL74HC174

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C to

-55

°C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

4.5

6.0

30

35

4.8

24

28

4.0

20

24

MHz

tPLH, tPHL

Maximum Propagation Delay, Clock to Q (Figures

1 and 4)

2.0

4.5

6.0

110

22

19

140

28

24

165

33

28

ns

tPHL

Maximum Propagation Delay , Reset to Q

(Figures 2 and 4)

2.0

4.5

6.0

110

21

19

140

28

24

160

32

27

ns

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

CIN

Maximum Input Capacitance

-

10

pF

Power Dissipation Capacitance (Per Enabled

Output)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption: PD=CPDVCC

2f+I

CCVCC

62

pF

TIMING REQUIREMENTS (C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C to

-55

°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time, Data to

Clock (Figure 3)

2.0

4.5

6.0

50

10

9

65

13

11

75

15

13

ns

th

Minimum Hold Time, Clock to

Data (Figure 3)

2.0

4.5

6.0

5

ns

trec

Minimum Recovery Time,

Reset Inactive to Clock (Figure

2)

2.0

4.5

6.0

5

ns

tw

Minimum Pulse Width, Clock

(Figure 1)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

tw

Minimum Pulse Width, Reset

(Figure 2)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

ns

同様の部品番号 - SL74HC174D

メーカー	部品番号	データシート	部品情報
System Logic Semiconduc...	SL74HC175	49Kb / 5P	Quad D Flip-Flop with Common Clock and Reset
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